参数资料
型号: EP1K50FI256
厂商: ALTERA CORP
元件分类: PLD
英文描述: LOADABLE PLD, PBGA256
封装: 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256
文件页数: 13/84页
文件大小: 2224K
代理商: EP1K50FI256
20
Altera Corporation
ACEX 1K Programmable Logic Family Data Sheet
Preliminary Information
LE Operating Modes
The ACEX 1K LE can operate in the following four modes:
s
Normal mode
s
Arithmetic mode
s
Up/down counter mode
s
Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The
MAX+PLUS II software, in conjunction with parameterized functions
such as LPM and DesignWare functions, automatically chooses the
appropriate mode for common functions such as counters, adders, and
multipliers. If required, the designer can also create special-purpose
functions that use a specific LE operating mode for optimal performance.
The architecture provides a synchronous clock enable to the register in all
four modes. The MAX+PLUS II software can set DATA1 to enable the
register synchronously, providing easy implementation of fully
synchronous designs.
Figure 11 shows the ACEX 1K LE operating modes.
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EP1K50FI256-1DX 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI256-1F 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI256-1P 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI256-1X 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI256-2 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256