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参数资料
| 型号： | EP1K50FI256 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA256 |
| 封装： | 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256 |
| 文件页数： | 45/84页 |
| 文件大小： | 2224K |
| 代理商： | EP1K50FI256 |
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Altera Corporation
5
Preliminary Information
ACEX 1K Programmable Logic Family Data Sheet
Development
13
Tools
Table 5 shows ACEX 1K device performance for more complex designs.
These designs are available as Altera MegaCoreTM functions.
Each ACEX 1K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.
ACEX 1K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers EPC1, EPC2, and EPC1441 configuration devices, which
configure ACEX 1K devices via a serial data stream. Configuration data
can also be downloaded from system RAM or via the Altera
MasterBlasterTM, ByteBlasterMVTM, ByteBlasterTM, or BitBlasterTM
download cables. (The ByteBlaster cable is obsolete and is replaced by the
ByteBlasterMV cable, which can program and configure 2.5-V, 3.3-V, and
5.0-V devices.) After an ACEX 1K device has been configured, it can be
reconfigured in-circuit by resetting the device and loading new data.
Because reconfiguration requires less than 40 ms, real-time changes can be
made during system operation.
ACEX 1K devices contain an interface that permits microprocessors to
configure ACEX 1K devices serially or in parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat an
ACEX 1K device as memory and configure it by writing to a virtual
memory location, simplifying device reconfiguration.
Table 5. ACEX 1K Device Performance for Complex Designs
Application
LEs
Used
Performance
Units
Speed Grade
-1
-2
-3
16-bit, 8-tap parallel finite impulse response (FIR)
filter
420
185
175
122
MSPS
8-bit, 512-point Fast Fourier transform (FFT)
function
1,854
47.4
57.8
76.5
s
100
82
62
MHz
a16450
universal asynchronous
receiver/transmitter (UART)
342
66
57
44
MHz
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50FI256-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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