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参数资料
| 型号： | EP1K50FI256 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA256 |
| 封装： | 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256 |
| 文件页数： | 80/84页 |
| 文件大小： | 2224K |
| 代理商： | EP1K50FI256 |
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Altera Corporation
81
Preliminary Information
ACEX 1K Programmable Logic Family Data Sheet
Development
13
Tools
During initialization, which occurs immediately after configuration, the
device resets registers, enables I/O pins, and begins to operate as a logic
device. The I/O pins are tri-stated during power-up, and before and
during configuration. Together, the configuration and initialization
processes are called command mode; normal device operation is called user
mode.
SRAM configuration elements allow ACEX 1K devices to be reconfigured
in-circuit by loading new configuration data into the device. Real-time
reconfiguration is performed by forcing the device into command mode
with a device pin, loading different configuration data, re-initializing the
device, and resuming user-mode operation. The entire reconfiguration
process requires less than 40 ms and can be used to reconfigure an entire
system dynamically. In-field upgrades can be performed by distributing
new configuration files.
Before and during configuration, all I/O pins (except dedicated inputs,
clock, or configuration pins) are pulled high by a weak pull-up resistor.
Conguration Schemes
The configuration data for an ACEX 1K device can be loaded with one of
five configuration schemes (see Table 59), chosen on the basis of the target
application. An EPC2, EPC1, or EPC1441 configuration device, intelligent
controller, or the JTAG port can be used to control the configuration of a
ACEX 1K device, allowing automatic configuration on system power-up.
Multiple ACEX 1K devices can be configured in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device. Additional
APEX 20K, APEX 20KE, FLEX 10K, FLEX 10KA, FLEX 10KE, ACEX 1K,
and FLEX 6000 devices can be configured in the same serial chain.
Table 59. Data Sources for ACEX 1K Configuration
Configuration Scheme
Data Source
Configuration device
EPC1, EPC2, or EPC1441 configuration device
Passive serial (PS)
BitBlaster, ByteBlaster, or ByteBlasterMV download cables, or
serial data source
Passive parallel asynchronous (PPA)
Parallel data source
Passive parallel synchronous (PPS)
Parallel data source
JTAG
BitBlaster or ByteBlasterMV download cables, or
microprocessor with a Jam File or JBC File
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50FI256-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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