Altera Corporation
39
Preliminary Information
ACEX 1K Programmable Logic Family Data Sheet
Development
13
Tools
Notes to tables:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this
frequency. The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency
during device operation. Simulation does not reflect this parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the tLOCK value is less than the time required for configuration.
(4)
The tJITTER specification is measured under long-term observation. The maximum value for tJITTER is 200 ps if
tINCLKSTB is lower than 50 ps.
I/O
Conguration
This section discusses the PCI pull-up clamping diode option, slew-rate
control, open-drain output option, and MultiVolt I/O interface for
ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via MAX+PLUS II
logic options. The MultiVolt I/O interface is controlled by connecting
VCCIO to a different voltage than VCCINT. Its effect can be simulated in the
MAX+PLUS II software via the Global Project Device Options dialog
box (Assign menu).
Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
5
ns
tF
Input fall time
5
ns
tINDUTY
Input duty cycle
40
60
%
fCLK1
Input clock frequency (ClockBoost clock
multiplication factor equals 1)
25
75
MHz
fCLK2
Input clock frequency (ClockBoost clock
multiplication factor equals 2)
16
37.5
MHz
fCLKDEV
Input deviation from user specification in
the MAX+PLUS II software (ClockBoost
clock multiplication factor equals 1)
25,000
PPM
tINCLKSTB Input clock stability (measured between
adjacent clocks)
100
ps
tLOCK
Time required for ClockLock or ClockBoost
to acquire lock
10
s
tJITTER
Jitter on ClockLock or ClockBoost-
generated clock
tINCLKSTB < 100
250
ps
tINCLKSTB < 50
200
ps
tOUTDUTY Duty cycle for ClockLock or ClockBoost-
generated clock
40
50
60
%