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| 型号： | EP1K50FI256 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA256 |
| 封装： | 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256 |
| 文件页数： | 19/84页 |
| 文件大小： | 2224K |
| 代理商： | EP1K50FI256 |
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Altera Corporation
ACEX 1K Programmable Logic Family Data Sheet
Preliminary Information
FastTrack Interconnect Routing Structure
In the ACEX 1K architecture, connections between LEs, EABs, and device
I/O pins are provided by the FastTrack Interconnect routing structure,
which is a series of continuous horizontal and vertical routing channels
that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The FastTrack Interconnect routing structure consists of row and column
interconnect channels that span the entire device. Each row of LABs is
served by a dedicated row interconnect. The row interconnect can drive
I/O pins and feed other LABs in the row. The column interconnect routes
signals between rows and can drive I/O pins.
Row channels drive into the LAB or EAB local interconnect. The row
signal is buffered at every LAB or EAB to reduce the effect of fan-out on
delay. A row channel can be driven by an LE or by one of three column
channels. These four signals feed dual 4-to-1 multiplexers that connect to
two specific row channels. These multiplexers, which are connected to
each LE, allow column channels to drive row channels even when all eight
LEs in a LAB drive the row interconnect.
Each column of LABs or EABs is served by a dedicated column
interconnect. The column interconnect that serves the EABs has twice as
many channels as other column interconnects. The column interconnect
can then drive I/O pins or another row’s interconnect to route the signals
to other LABs or EABs in the device. A signal from the column
interconnect, which can be either the output of a LE or an input from an
I/O pin, must be routed to the row interconnect before it can enter a LAB
or EAB. Each row channel that is driven by an IOE or EAB can drive one
specific column channel.
Access to row and column channels can be switched between LEs in
adjacent pairs of LABs. For example, a LE in one LAB can drive the row
and column channels normally driven by a particular LE in the adjacent
LAB in the same row, and vice versa. This flexibility enables routing
resources to be used more efficiently. Figure 13 shows the ACEX 1K LAB.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50FI256-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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