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| 型号： | EP20K100BC196-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA196 |
| 文件页数： | 11/68页 |
| 文件大小： | 975K |
| 代理商： | EP20K100BC196-2 |
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19
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
6.
Memories
This section describes the different memories in the AT90PWM2/2B/3/3B. The AVR architecture
has two main memory spaces, the Data Memory and the Program Memory space. In addition,
the AT90PWM2/2B/3/3B features an EEPROM Memory for data storage. All three memory
spaces are linear and regular.
6.1
In-System Reprogrammable Flash Program Memory
The AT90PWM2/2B/3/3B contains 8K bytes On-chip In-System Reprogrammable Flash memory
for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
4K x 16. For software security, the Flash Program memory space is divided into two sections,
Boot Program section and Application Program section.
The F lash memory has an endurance of at least 10,000 write/erase cycles. The
AT90PWM2/2B/3/3B Program Counter (PC) is 12 bits wide, thus addressing the 4K program
memory locations. The operation of Boot Program section and associated Boot Lock bits for
software protection are described in detail in “Boot Loader Support – Read-While-Write Self-Pro-
gramming” on page 265. “Memory Programming” on page 280 contains a detailed description
on Flash programming in SPI or Parallel programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory.
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
Figure 6-1.
Program Memory Map
6.2
SRAM Data Memory
Figure 6-2 shows how the AT90PWM2/2B/3/3B SRAM Memory is organized.
0x0000
0x0FFF
Program Memory
Application Flash Section
Boot Flash Section
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100BC196-3 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-1 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-2 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-3 | LOADABLE PLD, PBGA196 |
| EP20K100BC324-1 | LOADABLE PLD, PBGA324 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100BC356-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100BC356-1V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K100BC356-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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