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| 型号： | EP20K100BC196-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA196 |
| 文件页数： | 68/68页 |
| 文件大小： | 975K |
| 代理商： | EP20K100BC196-2 |
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Altera Corporation
9
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
MegaLAB Structure
APEX 20K devices are constructed from a series of MegaLAB structures.
Each MegaLAB structure contains 16 logic array blocks (LABs), one ESB,
and a MegaLAB interconnect, which routes signals within the MegaLAB
structure. In the EP10K1000E and EP10K1500E device, MegaLAB
structures contain 24 LABs. Signals are routed between MegaLAB
structures and I/O pins via the FastTrack Interconnect. In addition, edge
LABs can drive I/O pins through the local interconnect. Figure 2 shows
the MegaLAB structure.
Figure 2. MegaLAB Structure
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus Compiler places associated logic within an LAB or adjacent
LABs, allowing the use of a fast local interconnect for high performance.
Figure 3 shows the APEX 20K LAB.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
ESB
MegaLAB Interconnect
Local
Interconnect
To Adjacent
LAB or IOEs
LABs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
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PDF描述 |
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| EP20K100BC196-3 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-1 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-2 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-3 | LOADABLE PLD, PBGA196 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100BC356-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100BC356-1V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K100BC356-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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