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| 型号： | EP20K100BC196-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA196 |
| 文件页数： | 45/68页 |
| 文件大小： | 975K |
| 代理商： | EP20K100BC196-2 |
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Altera Corporation
5
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
General
Description
APEX 20K devices are the first PLDs designed with the MultiCore
architecture, which combines the strengths of LUT-based and product-
term-based devices with an enhanced memory structure. LUT-based logic
provides optimized performance and efficiency for data-path, register-
intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths,
such as complex state machines. LUT- and product-term-based logic
combined with memory functions and a wide variety of MegaCore and
AMPP functions make the APEX 20K architecture uniquely suited for
System-on-a-Programmable-Chip design. Applications historically
requiring a combination of LUT-, product-term-, and memory-based
devices can now be integrated into one APEX 20K device.
APEX 20KE devices are a superset of APEX 20K devices and include
additional features such as advanced I/O standard support, CAM,
additional global clocks, and enhanced ClockLock clock circuitry. In
addition, APEX 20KE devices extend the APEX 20K family to one million
gates. APEX 20KE devices are denoted with an “E” suffix in the device
name (e.g., the EPF20K1000E is an APEX 20KE device). Table 7
summarizes the features included in APEX 20K and APEX 20KE devices.
Table 5. APEX 20K QFP, BGA & PGA Package Sizes
Feature
144-Pin TQFP 208-Pin QFP 240-Pin QFP 356-Pin BGA 652-Pin BGA 655-Pin PGA
Pitch (mm)
0.50
1.27
–
Area (mm2)
484
936
1,197
1,225
2,025
3,906
Length
× Width
(mm
× mm)
22
× 22
30.6
× 30.6
34.6
× 34.6
35
× 35
45
× 45
62.5
× 62.5
Table 6. APEX 20K FineLine BGA Package Sizes
Feature
196-Pin
324-Pin
484-Pin
672-Pin
1,020-Pin
Pitch (mm)
1.00
Area (mm2)
225
361
529
729
1089
Length
× Width
(mm
× mm)
15
× 15
19
× 19
23
× 23
27
× 27
33
× 33
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100BC196-3 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-1 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-2 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-3 | LOADABLE PLD, PBGA196 |
| EP20K100BC324-1 | LOADABLE PLD, PBGA324 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100BC356-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100BC356-1V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K100BC356-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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