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参数资料
| 型号： | FDG6318PZ |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/9页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH DUAL 20V SC70-6 |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品变化通告： | Mold Compound Change 12/Dec/2007 Mold Compound Change 07/May/2008 |
| 标准包装： | 3,000 |
| FET 型： | 2 个 P 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 20V |
| 电流 - 连续漏极(Id) @ 25° C： | 500mA |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 780 毫欧 @ 500mA，4.5V |
| Id 时的 Vgs(th)（最大）： | 1.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 1.62nC @ 4.5V |
| 输入电容 (Ciss) @ Vds： | 85.4pF @ 10V |
| 功率 - 最大： | 300mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 供应商设备封装： | SC-70-6 |
| 包装： | 带卷 (TR) |
Electrical Characteristics T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B VDSS
I DSS
I GSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 μ A, V GS = 0V
V GS = ? 16V , V GS = 0V
V GS = ± 12V , V GS = 0V
-20
-
-
-
-
-
-
-3
± 10
V
μ A
μ A
On Characteristics
V GS(TH)
r DS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
V GS = V DS , I D = -250 μ A
I D = -0.5A, V GS = -4.5V
I D = -0.4A, V GS = -2.5V
-0.65
-
-
-0.9
5 8 0
910
-1.5
7 8 0
1200
V
m ?
Dynamic Characteristics
C ISS
C OSS
C RSS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = -10V, V GS = 0V,
f = 1MHz
-
-
-
85.4
24.9
8.83
-
-
-
pF
pF
pF
Q g(TOT)
Q g(-2.5)
Q gs
Q gd
Total Gate Charge at -4.5V
Total Gate Charge at -2.5V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V GS = 0V to -4.5V
V GS = 0V to -2.5V
V DD = -10V
I D = -0.5A
I g = 1.0mA
-
-
-
-
1.08
0.67
0.21
0.33
1.62
1.0
-
-
nC
nC
nC
nC
Switching Characteristics (V GS = -4.5V)
t ON
t d(ON)
Turn-On Time
Turn-On Delay Time
-
-
-
10
35
-
ns
ns
t r
t d(OFF)
t f
t OFF
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
V DD = -10V, I D = -0.5A
V GS = -4.5V, R GS = 120 ?
-
-
-
-
13
40
24
-
-
-
-
96
ns
ns
ns
ns
Drain-Source Diode Characteristics
V SD
t rr
Q RR
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
I SD = -0.5A
I SD = -0.5A, dI SD /dt = 100A/ μ s
I SD = -0.5A, dI SD /dt = 100A/ μ s
-
-
-
-0.9
-
-
-1.2
22
16
V
ns
nC
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the center drain pad. R θ JC is guaranteed by design while R θ CA is determined by user’s board design. R θ JA = 415 o C/W when mounted on a 1inch 2 copper pad.
?2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
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