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参数资料
| 型号： | FDG6318PZ |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 7/9页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH DUAL 20V SC70-6 |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品变化通告： | Mold Compound Change 12/Dec/2007 Mold Compound Change 07/May/2008 |
| 标准包装： | 3,000 |
| FET 型： | 2 个 P 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 20V |
| 电流 - 连续漏极(Id) @ 25° C： | 500mA |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 780 毫欧 @ 500mA，4.5V |
| Id 时的 Vgs(th)（最大）： | 1.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 1.62nC @ 4.5V |
| 输入电容 (Ciss) @ Vds： | 85.4pF @ 10V |
| 功率 - 最大： | 300mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 供应商设备封装： | SC-70-6 |
| 包装： | 带卷 (TR) |
SABER Electrical Model
REV January 2003
template fdg6318pz n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 7.7e-11, nl=1.277, rs = 1e-3, trs1 = 2.8e-1, trs2 = 3e-4, xti=0, cjo = 3.9e-11, ikf=0.5, tt = 33e-9, m = 0.50)
dp..model dbreakmod = (rs = 5.3e-1, trs1 = 5.5e-3, trs2 = -9.0e-5)
dp..model dplcapmod = (cjo = 0.5e-10, isl=10e-30, nl=10, m=0.55)
m..model mmedmod = (type=_p, vto = -1.17, kp=0.6, is=1e-30, tox=1)
m..model mstrongmod = (type=_p, vto = -1.45, kp = 1.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_p, vto = -0.99, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0.2)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = 0.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.1)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.4)
ESG
LDRAIN
c.ca n12 n8 = 0.6e-10
c.cb n15 n14 = 1.1e-10
10
8
6
+
5
DRAIN
2
c.cin n6 n8 = 0.75e-10
RSLC1
RLDRAIN
dp.dbody n5 n7 = model=dbodymod
RSLC2
51
+
dp.dbreak n7 n11 = model=dbreakmod
dp.dplcap n10 n6 = model=dplcapmod
ISCL
50
EBREAK
17
18
18 +
9
20
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 0.47e-9
l.lsource n3 n7 = 0.47e-9
GATE
1
LGATE
RLGATE
DPLCAP
EVTEMP
RGATE
22
6
EVTHRES
+ 19
8
RDRAIN
16
21
MMED
MSTRO
MWEAK
DBREAK
11
DBODY
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
CIN
8
RSOURCE
7
LSOURCE
SOURCE
3
RLSOURCE
res.rgate n9 n20 = 12.4
res.rldrain n2 n5 = 10
res.rslc1 n5 n51= 1e-6, tc1 = 3.7e-3, tc2 =7.8e-6
EGS
res.rslc2 n5 n50 = 1e3
res.rbreak n17 n18 = 1, tc1 = 5.5e-4, tc2 = -1e-7 S1A
res.rdrain n50 n16 = 280e-3, tc1 = 2.8e-3, tc2 = 4.9e-6 12 13 14
S1B
res.rlgate n1 n9 = 4.7
CA
res.rlsource n3 n7 = 4.7 +
res.rsource n8 n7 = 190e-3, tc1 = 3e-3, tc2 =5.2e-6
8 13
13
6
8
S2A
15
S2B
CB
EDS
+
5
8
14
8
17
RBREAK
IT
18
RVTEMP
19
VBAT
+
22
res.rvtemp n18 n19 = 1, tc1 = -5.5e-4, tc2 = -1e-9
res.rvthres n22 n8 = 1, tc1 = 9e-4, tc2 = 3e-7
spe.ebreak n5 n11 n17 n18 = -23.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n5 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/20))** 2.5))
}
}
?2003 Fairchild Semiconductor Corporation
RVTHRES
FDG6318PZ Rev. B
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