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| 型号： | GT-48004A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| 中文描述： | 四端口交换式快速以太网控制器（四端口，交换式快速以太网控制器） |
| 文件页数： | 10/106页 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
11
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
2.2
Pin Functions and Assignment
S y mbol
Ty p e
D esc ri pti o n
PCI Bus Interface
Rst*
I
RESET: Active LOW. Rst* must be asserted for at least 10 PCI clock cycles.
When in the reset state, all PCI output pins are tristated and all open drain sig-
nals are floated. Following Rst* deassertion, the GT-48004A clears the internal
buffers and initializes the address table in the DRAM. The address table initial-
ization takes 165,000 CLK cycles to complete. Any incoming packets during
the address table initialization, are ignored.
PClk
I
Clock: Provides the timing for the GT-48004A internal units. All functional
units except for the serial interfaces use this clock.Clk also provides timing for
PCI bus transactions. The clock frequency is 50MHz (target of 66MHz).
Req0/1*
O
Bus Request0/1: Asserted by the individual 2 port Fast Ethernet units within
GT-48004A to indicate to the PCI bus arbiter that this unit requires mastership
of the bus.
Note that even a 4 port single chip system will need to provide
external PCI arbitration between the two on-chip units.
Gnt0/1*
I
Bus Grant 0/1: Indicates to the individual Fast Ethernet units GT-48004A that
access to the PCI bus is granted.
PErr*
I/O
Parity Error: Asserted when a data parity error is detected on the PCI bus.
SErr*
O
System Error: Asserted by the GT-48004A when an address parity error is
detected on the PCI bus. The GT-48004A asserts SErr* two cycles after the
failing address. This output features an open-collector driver.
IDSel0/1
I
Initialization Device Select 0/1: Asserted by a PCI bus master to gain access
to the GT-48004A’s configuration headers for each Fast Ethernet unit during
configuration read/write transactions.
DevSel*
I/O
Device Select: Asserted by the target of the current PCI access. When the
GT-48004A is a bus master, it expects the target to assert DevSel* within 5
bus cycles, confirming the access. If the target does not assert DevSel* within
the required bus cycles, the GT-48004A aborts the cycle. As a target, the GT-
48004A asserts DevSel* as a “medium speed” PCI device (two cycles after the
assertion of Frame*).
Stop*
I/O
Stop: Indicates that the current target is requesting the bus master to stop the
current transaction. As a master, the GT-48004A responds to the assertion of
Stop* by either disconnecting, retrying, or aborting. As a target, the GT-
48004A asserts Stop* to force a retry.
Frame*
I/O
Cycle Frame: Asserted by the GT-48004A to indicate the beginning and dura-
tion of a master transaction. Frame* is asserted to indicate the beginning of the
cycle. While Frame* is asserted, data transfer continues. Frame* is deasserted
to indicate that the next data phase is the final data phase transaction. Frame*
is monitored when the GT-48004A acts as a target, to detect a configuration or
memory transaction.
Par
I/O
Parity: Calculated by the GT-48004A as an even parity bit for the AD[31:0]
and CBE[3:0]* lines.
TRdy*
I/O
Target Ready: Indicates the target agent’s ability to complete the current data
phase of the transaction. A data phase is completed on any clock when both
TRdy* and IRdy* are asserted. Wait cycles are inserted until both IRdy* and
TRdy* are asserted together.
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