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参数资料
| 型号： | GT-48004A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| 中文描述： | 四端口交换式快速以太网控制器（四端口，交换式快速以太网控制器） |
| 文件页数： | 14/106页 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
15
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
DisWD*
I
Disable Watchdog Timer: Active LOW. DisWD* controls the enabling
(HIGH) or disabling (LOW) of the Tx Watchdog Timer on all ports.
DisBufThr*
I
Buffer Threshold: Active LOW. This pin externally enables or disables the
buffer threshold. When HIGH, the buffers allocated to the ports and the PCI
are limited to the number written in the Rx Buffer Threshold Register. When
LOW, the buffers are dynamically allocated to the ports and the PCI bus (i.e.
there is no limitation on the buffers’ allocation.)
Limit4
I
Backoff Algorithm: This pin selects the number of retransmit attempts after a
collision will occur before the back-off algorithm is restarted. When LOW, 16
retransmit attempts after a collision must occur before the back-off algorithm is
restarted (802.3 standard). When HIGH, 4 retransmit attempts after a collision
must occur before the back-off algorithm is restarted (more aggressive.)
SkipInit*
I
Skip Initialization Stage: Active LOW. This pin controls the initialization stage
of the GT-48004A. When asserted, the GT-48004A skips the initialization
stage (clearing the address table which is stored in the DRAM), upon the deas-
sertion of Rst*. This pin is typically used for testing and the default state is to
pull this pin HIGH.
VLAN
I
VLAN Enable: Active HIGH. This pin enables VLAN support in the GT-48004A
when connected to VCC. Connect to GND to disable VLAN mode.
Priority
I
Priority Enable: Active HIGH. This pin enables priority support in the GT-
48004A when connected to VCC. Connect to GND to disable priority mode.
JTAG
JTRST*
I
JTAG Reset: Asynchronous reset to test logic.
JTCLK
I
JTAG Clock: Clock for test logic. JTMS and JTDI are received on the rising
edge, JTDO is driven from the falling edge. This signal determines the shifting
rate.
JTMS
I
JTAG Mode Select: A broadcast signal which controls test logic operation.
JTDI
I
JTAG Data In: Serial data input.
JTDO
O
JTAG Data Out: Serial data output. Tri-state changes on negative change of
JTCLK.
S y mbol
Ty p e
D esc ri pti o n
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