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| 型号： | GT-48004A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| 中文描述： | 四端口交换式快速以太网控制器（四端口，交换式快速以太网控制器） |
| 文件页数： | 12/106页 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
13
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
TxD3[3:0]
O
Transmit Data 3: Outputs the Port3 Transmit Data. Synchronous to TxClk[3].
Col[3:0]
I
Collision Detect: Active HIGH. Indicates a collision has been detected on the
wire. This input is ignored in full-duplex mode, and in half-duplex mode when
TxEn of the same port is LOW. Col is not synchronous to any clock.
RxD0[3:0]
I
Receive Data 0: Port 0 Receive Data. Synchronous to RxClk[0].
RxD1[3:0]
I
Receive Data 1: Port 1 Receive Data. Synchronous to RxClk[1].
RxD2[3:0]
I
Receive Data 2: Port 0 Receive Data. Synchronous to RxClk[2].
RxD3[3:0]
I
Receive Data 3: Port 1 Receive Data. Synchronous to RxClk[3].
RxEr[3:0]
I
Receive Error. Active HIGH. Indicates that an error was detected in the
received frame. This input is ignored when RxDV for the same port is inactive.
RxClK[3:0]
I
Receive Clock. Provides the timing reference for the transfer of the RxDV,
RxD, RxEr signals (per port). Operates at either 25 MHz (100Mbps) or 2.5
MHz (10Mbps). The nominal frequency of RxClk (per port) should match the
nominal frequency of that port’s TxClk.
RxDV[3:0]
I
Receive Data Valid: Active HIGH. Indicates that valid data is present on the
RxD lines. Synchronous to RxClk. This input is ignored when it represents
loopback of the transmitted packet in 10BaseT mode half-duplex.
CrS[3:0]
I
Carrier Sense: Active HIGH. Indicates that either the transmit or receive
medium is non-idle. CrS is not synchronous to any clock.
MDC
O
Management Data Clock: 1 MHz clock. Provides the timing reference for the
transfer of the MDIO 0/1 signal. This output may be connected to the PHY
devices of all ports.
MDIO0/1
I/O
Management Data Input/Output 0/1: This bidirectional line is used to transfer
control information and status between the PHY and the GT-48004A. It con
forms with IEEE Std 802.3. This signal may be connected to the PHY devices
of both ports. When not in use, this pin must be connected to a pull-down resis-
tor. Each 2 port Fast Ethernet unit has its own MDIO line.
Miscellaneous Interface Pins
EnAutoNeg*
I
Enable Auto-negotiation: Active LOW. The GT-48004A controls the auto-
negotiation process and configures both ports to the correct speed and duplex
as resolved by each port’s PHY. When HIGH, auto-negotiation is disabled and
the duplex setting of both ports is set based on the RESET configuration. See
Section 13.3.3 for more information on Auto-negotiation Control Per Port.
AForceLinkPass*
I/O
Fast Ethernet Unit 0 (“A”) Force Link Pass: Active LOW. This pin is sam-
pled on Rst*. When connected HIGH, the link status of ports 0 and 1 is read
through the SMI (MDC/MDIO interface) from the PHY devices (register#1,
bit#2). When connected LOW, the link status of ports 0 and 1 remains in the
“link is up” state regardless of the PHY’s link bit value. This pin should be con-
nected to either a pull-up (normally) or a pull-down resistor (to force the link
pass). Following Rst* deassertion, this pin becomes an output (unused - value
is undefined).
S y mbol
Ty p e
D esc ri pti o n
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