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| 型号： | GT-48004A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| 中文描述： | 四端口交换式快速以太网控制器（四端口，交换式快速以太网控制器） |
| 文件页数： | 93/106页 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
87
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Time Out Counter, Offset: 0x4c
23.3
Port MIB Counters (2 Blocks), Offset: 0x040000 - 0x0400ac
The CPU must read all of the MIB counters during initialization in order to reset the counters to ‘0’. All counters are 32-
bits. The CPU must access the counters using single datum transactions (burst reads/writes are not allowed.) MIB
counters can be cleared by reading, or left intact after a read based on the MIB Clear Mode (bit 30 in the Global Com-
mand Register.) During initialization, the CPU must read all of the MIB counters in order to reset the counters to ‘0’. The
counters will only be reset to ‘0’ if MIBClrMode (bit 30 of the Global Control Register) is set to ‘0’ (default). If MIBClr-
Mode bit is ‘1’, reading the MIB counters will have no effect.
Table 35 lists definitions for terms used in the counter descriptions.
Table 35: Definitions Used in Counter Descriptions
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
7:0
TimeOut0
Specifies in PCI clock units the number of clocks the
GT-48004A holds the PCI bus before the generation
of Retry termination. Used for the first data transfer.
0x0f (16 clocks)
15:8
TimeOut1
Specifies in PCI clock units the number of clocks the
GT-48004A holds the PCI bus before the generation
of Retry termination. Used for data transfers following
the first data.
0x07 (8 clocks)
23:16
RetryCounter
Specifies the number of retries the GT-48004A
attempts to do in the PCI before aborting the transac-
tion. Value of 0x0 disable this counter (unlimited
retries).
0xFF (256 times)
Te rm
De fin i t i on
Packet Data Section
All data bytes in the packet following the SFD until the end of the packet
Packet Data Length
The number of data bytes in the packet data section
Data Octet
A single byte from the packet data section
Nibble
4 bits (half byte) of a data octet
Misaligned Packet
A packet with an odd number of nibbles
Received Good
Packet
A received packet which is not rejected and enters the switching core to be trans-
mitted later
Transmitted Good
Packet
Any transmitted packet from the GT-48004A
Collision Event
A collision has been detected until than 576 bit times into the transmitted packet
after TxEn.
Late Collision Event
A collision has been detected later than 576 bit times into the transmitted packet
after TxEn.
Rx Error Event
The input RX_ERR has been asserted
Dropped Packet
A received packet which is ignored due to lack of available receive buffers (port is
in buffer_full state)
Local Packet
A received packet whose destination address is mapped to the receiving port
Rejected Packet
A received packet which is not forwarded due to error such as bad CRC, Rx Error
Event, Invalid size (too short or too long).
MIBCtrMode
Bit 26, MIBCtrMode, of the Global Control Register (offset 0x140028)
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