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参数资料
| 型号： | GT-48004A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| 中文描述： | 四端口交换式快速以太网控制器（四端口，交换式快速以太网控制器） |
| 文件页数： | 50/106页 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
48
12.
Fast PCI Bus Operation
The GT-48004A can act as either a master initiating a PCI bus operation, or as a target responding to a PCI bus oper-
ation. The GT-48004A is enabled to both master the PCI bus and respond to memory accesses after RESET.
The GT-48004A has two sets of internal registers that are accessible through the PCI interface for each FEU. Internal
control registers for the GT-48004A are memory mapped and accessible through standard PCI read/write operations.
PCI control registers are accessible through PCI configuration cycles.
12.1
Separate Logical PCI Interfaces for Each FEU
Each FEU within a GT-48004A has a separate logical PCI interface. This means that there are separate Req/Gnt* pairs
and a separate IdSel for each FEU. This also means that there are two separate Configuration Headers, Register
banks, etc. From both the software and hardware standpoint, it is as if the GT-48004A has two physical PCI devices in
a single package.
12.2
Interfacing Management Processors to Fast PCI
The Fast PCI bus required by the GT-48004A runs up to 66MHz. To connect a management processor, you must have
a PCI interface chip capable of running at this speed. Galileo currently offers two system controller products which
incorporate Fast PCI interfaces as well as a memory controller (and all other core logic):
The GT-64120 interfaces all 64-bit bus MIPs processors (R4700 through R5000) to the GT-48004A. The GT-
64120 includes two 66MHz PCI interfaces as well as a 75MHz CPU interface and SDRAM controller.
The GT-64111 interfaces 32-bit bus MIPS processors (R4640, RM5230 and Vr4300) to the GT-48004A. The
GT-64111 includes a single 66MHz PCI interfaces as well as a 66MHz CPU interface and EDO DRAM control-
ler. The GT-64111 is the more appropriate choice for cost sensitive applications.
It is possible to run the GT-48004A at 33MHz on the PCI bus, however, doing so will not realize any performance ben-
efit over the GT-48002A.
12.3
PCI Configuration Header Registers
The GT-48004A’s PCI configuration registers are located in the standard PCI configuration header locations. Access to
these registers is through PCI configuration reads/writes with the specific IdSel0/1 signal asserted. PCI configuration
registers control PCI functions and return PCI information (device/vendor ID, etc.) Note that there are two separate
configuration headers in the GT-48004A; one for FEU0 and the other for FEU1.
12.4
Accessing DRAM and Internal Registers through the PCI Interface
All GT-48004A internal control registers and the local DRAM are mapped into PCI memory space. Each FEU in the
GT-48004A looks at PCI address bits 31:22 to determine if it is the target for the current cycle. This results in a decode
region of 4Mbytes per FEU in a GT-48004A. Bit 21 of the address is used by the FEU to subdecode on-chip between
accesses to DRAM and accesses to the internal registers. Bits 20:0 are used to select a specific register or memory
location. Register addresses given in this document refer to the value of bits 20:0 in the PCI address. The GT-48004A
expects data in little-endian format, as is required by the PCI specification.
The GT-48004A acts as a “medium speed” decode device, returning DevSel* in 2 clocks.
12.5
Fast PCI Bandwidth/Performance Issues
The fast PCI bus has an ideal maximum bandwidth of just under 264Mbytes/sec at 66MHz (about 2 gigabits per sec-
ond.) In systems with many GalNet devices the bandwidth available on the PCI bus can become a performance limita-
tion.
There are several factors that reduce the maximum achievable bus bandwidth:
Aggressiveness of the PCI arbiter. For example, the use of hidden arbitration can save cycles between adja-
cent accesses and improve overall bandwidth. Simpler arbiters will degrade bandwidth as cycles that could be
used for data transfer are used for arbitration.
The GalNet protocol does involve some overhead when compared to raw data transfer.
While performance in any given system is impossible to estimate due to design differences, Galileo Technology has
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