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| 型号： | GT-48004A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| 中文描述： | 四端口交换式快速以太网控制器（四端口，交换式快速以太网控制器） |
| 文件页数： | 13/106页 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
14
BForceLinkPass*
I/O
Fast Ethernet Unit 1 (“B”) Force Link Pass: Active LOW. This pin is sam-
pled on Rst*. When connected HIGH, the link status of the ports 2 and 3 is
read through the SMI (MDC/MDIO interface) from the PHY devices (regis-
ter#1, bit#2). When connected LOW, the link status of ports 2 and 3 remains in
the “link is up” state regardless of the PHY’s link bit value. This pin should be
connected to either a pull-up (normally) or a pull-down resistor (to force the link
pass). Following Rst* deassertion, this pin becomes an output (unused - value
is undefined).
LEDMode
I
LED Mode Select: Affects Port status LED, LEDClk frequency and LED ON
time values. For more information, see Section 18.
0 - select LEDMode 0
1 - select LEDMode 1
LEDData 0/1
O
LED Data: LED indicators (Link Status, Receive, Transmit, Collision,
Unknown, Port Sniffer, and Half/Full Duplex) of each port. The data is shifted
out in 128 bit long frames using the LEDClk and LEDStb pins.
Each 2 port Fast Ethernet unit has its own LEDData pin.
LEDStb 0/1
O
LED Strobe: Indicates the beginning of valid data frame on the LEDData pin.
Each 2 port Fast Ethernet unit has its own LEDStb pin.
LEDClk0/1
O
LED Clock 0/1: 1 MHz clock (at LEDMode 0), 202 KHz clock (at LEDMode 1).
This output is used to clock the LEDStb and LEDData outputs. During RESET,
LEDClk is tristated. Each 2 port Fast Ethernet unit has its own LED clock.
LEDRxBufFull*[3:0]
O
LED Receive Buffer Full: Active LOW LED output Indicates (per port)
receive buffer full condition (programmable limit exceeded).
An external driver is required to drive LEDs.
RstQueue*
I
Reset Transmit Queues: When asserted, all internal transmit and receive
queues are cleared. All GT-48004A state machines are moved to their initial
state.
EnDev*
I
Enable Device: Enables serial and PCI ports. When asserted LOW, all serial
ports and the PCI port are active. When deasserted, the ports and the PCI are
disabled (see Section 4.1).
Scan*
I
Scan: This pin together with TriState* indicate the GT-48004A mode of opera-
tion as follows:
Factory test modes are reserved and are not to be used in-system. Failure to
observe this restriction could result in damage to the device.
TriState*
I
Tri-State: This pin together with Scan* indicate the GT-48004A mode of oper-
ation as described above.
Sy m b ol
Ty p e
De s c ri pti o n
Sc an*
Tr i S t a t e *
Mode
1
Normal operation
0
1
Factory test mode (reserved)
1
0
The GT-48004A drives all out-
puts and I/O pins to high imped-
ance.
0
Factory test mode (reserved)
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