- 您现在的位置：买卖IC网 > PDF目录67672 > GT-48004A (Galileo Technology Services, LLC) Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) PDF资料下载
参数资料
| 型号： | GT-48004A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| 中文描述： | 四端口交换式快速以太网控制器（四端口，交换式快速以太网控制器） |
| 文件页数： | 68/106页 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页当前第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
64
Setting this bit should also generate a processor interrupt. The Interrupt Cause register may be read to determine the
state of the Ease_Registers, and may be written to clear the interrupt condition described above. It is possible for the
CPU to mask the interrupt condition as well as clear the interrupt condition. The GT-48004A implements a mask bit in
the Interrupt Mask register for each EASE status bit in the Interrupt Cause register. Masking and clearing the interrupts
are executed in a way that is consistent with the other interrupts supported by the GT-48004A.
Interrupt Cause Register, Offs e t: 0x0 44
Interrupt Mask Register, Offset: 0x 048
16.5
Sampled Packet Indication
Sampled packets are copied into the CPU’s receive buffers using the same mechanism as normal receive packets. The
only difference, from the CPU’s point of view, is that the GT-48004A will put an indication in the first word of the receive
buffer which identifies the packet as a sample. The sample indication bits specify which ports on the particular GT-
48004A the sample is associated with. It is possible for a single sample to be associated with more than one port at a
time. For example, a broadcast packet flooded to all ports may be sampled on several ports if each of their skip counters
had previously been decremented to zero.
Each GT-48004A device operates independently, so it is possible for the CPU to receive the same sample from different
GT-48004A devices. For example, a broadcast packet flooded to all ports in the system may be sampled by several GT-
48004As at the same time. Each sample will result in a separate copy of the packet being sent to the CPU. It is also
possible to sample a packet which would normally be received by the CPU. In this case, only a single copy of the packet
can be sent to the CPU. The CPU should be responsible for determining if a sampled packet should also be accepted
as a normal receive packet. In the case where a normally received packet is also a sample from multiple GT-48004A
devices (e.g. a broadcast packet), the GT-48004A must provide an indication which allows the CPU to avoid processing
duplicate packets. This indication is provided by the GT-48004A which actually received the packet from an external link.
An additional bit in the packet header indicates that the sample packet was originally received from an external link to
the CPU as opposed to the PCI system bus. Other GT-48004A devices which sampled the flooded packet only because
it was received from the PCI interface and is being transmitted on a port whose internal counter was decremented to
zero will not have this indication. These samples are “pure” samples and the CPU will know that it should not process
the packet as a normally received packet.
The first word in each 2K block holding the packet to CPU contains the following bits:
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
19
EaseReg0Empty
Ease_Register of port 0 is empty
0x0
20
EaseReg1Empty
Ease_Register of port 1 is empty
0x0
27
ErrorSASent
Error_Source message sent to CPU
0x0
other
various interrupt cause
bits
left unchanged. See register section for details
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
27:19
MaskBits
Mask the CPU interrupt line for the appropriate bits in the Interrupt
Cause register.
0x0
other
various interrupt mask
bits
left unchanged. See register section for details
0x0
相关PDF资料 |
PDF描述 |
|---|---|
| GT-48006A | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、双端口10/100Mbps以太网桥式/交换式控制器) |
| GT-48207 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
| GT-48208 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
| GT-48212 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
| GT-64010A | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(带PCI接口用于R4XXX/ R5000 系列 CPUs的系统控制器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GT482 | 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:Cap Ceramic 82pF 3000V SL 5% (12 X 6mm) Radial 9.5mm 85°C |
| GT48212-A6-PBB1C000 | 制造商:Marvell 功能描述: |
| GT48212-A6-PBB-C000 | 制造商:Marvell 功能描述:12 PORT E + 2 PORT FE SWITCH (MANAGED) - Trays |
| GT48300-A1-BBE1C083 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083 |
| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
发布紧急采购，3分钟左右您将得到回复。