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| 型号： | GT-48004A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| 中文描述： | 四端口交换式快速以太网控制器（四端口，交换式快速以太网控制器） |
| 文件页数： | 71/106页 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
67
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
17.
DRAM Interface and Usage
The GT-48004A includes direct support two separate 1-2Mbyte arrays of 35nS EDO DRAM. The performance of 35nS
EDO satisfies the required bandwidth for data transfer, address recognition and Tx descriptor fetch/update. The DRAM
interface is entirely glueless. All accesses are performed as 32-bits. The DRAM interface is designed for 35ns EDO
DRAMs and all timings are guaranteed to work with these devices. Refresh is performed automatically by the GT-
48004A.
NOTE: 35ns EDO DRAMs are available from several vendors including Silicon Magic (www.simagic.com) and
Mosel-Vitelic (www.mosel-vitelic.com).
Each FEU within the GT-48004A requires its own separate DRAM array. This is more efficient than a single 64-bit wide
array as it allows address lookups and packet transfers to occur independently.
Each FEU requires about 300Kbytes of the DRAM for the address table and other private data structures. The remain-
der is used for packet buffers. Following power-up or system RESET, the GT-48004A device creates the MAC Address
Table in DRAM, and initializes all locations in the table to indicate that invalid entries exist in all locations.
Galileo recommends using DRAM with 256K x 16 configuration. When using this configuration, 2 DRAM chips are
required for 1 MByte, and 4 DRAM chips are required for 2 MBytes. If 1 MByte is selected, RAS0* should be connected
to 2 DRAM chips while RAS1* should be left unconnected.
If 2 MBytes is selected, RAS0* will control the first 1MB bank, while RAS1* will activate the second 1MB bank.
DData[31:0], DAddr[8:0], CAS*, and WE* should be connected to both banks.
Using 1 or 2 MBytes of DRAM is entirely up to the architect. 2MBytes increases the size of the Rx Buffer space. This
performance advantage must be weighed against the cost of additional memory.
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相关代理商/技术参数 |
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| GT482 | 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:Cap Ceramic 82pF 3000V SL 5% (12 X 6mm) Radial 9.5mm 85°C |
| GT48212-A6-PBB1C000 | 制造商:Marvell 功能描述: |
| GT48212-A6-PBB-C000 | 制造商:Marvell 功能描述:12 PORT E + 2 PORT FE SWITCH (MANAGED) - Trays |
| GT48300-A1-BBE1C083 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083 |
| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
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