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参数资料
| 型号： | HSP50415VIZ |
| 厂商： | Intersil |
| 文件页数： | 14/29页 |
| 文件大小： | 0K |
| 描述： | IC MODULATOR PROGRAMABLE 100MQFP |
| 标准包装： | 66 |
| 功能： | 调制器 |
| 封装/外壳： | 100-BQFP |
| 包装： | 托盘 |
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HSP50415
Voltage Reference
4
The internal voltage reference of the device has a nominal
3
2
1
0
-1
-2
-3
ISF
SINC
value of + 1.2V with a ± 10ppm / o C drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1 μ F capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin selects
the reference. The internal reference can be selected if
REFLO is tied low (ground). If an external reference is
desired, then REFLO should be tied high (the analog supply
voltage) and the external reference driven into REFIO. The full
scale output current of the converter is a function of the
voltage reference used and the value of R SET . I OUT should
-4
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
be within the 2mA to 20mA range, though operation below
2mA is possible, with performance degradation.
NORMALIZED FREQUENCY
FIGURE 18. X/SIN(X) FILTER RESPONSE
I/Q Gain Imbalance Correction Stage
Following the X/SIN(X) filter pair is a gain stage where I and
Q are scaled independently. The programmable gain
consists of a 10-bit scale factor and a 10-bit DC offset. The
equation for the gain is as follows:
dataOut<15:0> = (dataIn<15:0> * (1.0 +/-
0.00SSSSSSSSSS)) +/- 0.00DDDDDDDDDD
V FSADJ and V REFIO will be equivalent except for a small
offset voltage. If the internal reference is used, V FSADJ will
equal approximately 1.2V on the FSADJ. If an external
reference is used, V FSADJ will equal the external reference.
The calculation for I OUT (Full Scale) is:
I OUT (Full Scale) = (V FSADJ /R SET ) X 32.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91k Ω R SET resistor,
then the input coding to output current is shown in Table 5.
TABLE 5. INPUT CODING vs OUTPUT CURRENT
Where SSSSSSSSSS denotes the 10-bit scale factor and
DDDDDDDDDD is the 10-bit DC offset value. The scale
factor may be optionally added or subtracted from 1.0 and
the DC offset may optionally be added or subtracted to the
result of the scale operation.
INPUT CODE <D11-D0>
11 11111 11111
10 00000 00000
00 00000 00000
I/QOUTA (mA)
20
10
0
I/QOUTB (mA)
0
10
20
For a gain of 1.0 through this stage, program the scale factor
to 0x000 and the DC offset to 0x000 for both the I and Q
values. The output is rounded to either 14-bits or 12-bits.
The rounding options are programmable as shown in
Table 4.
TABLE 4. IQ GAIN CORRECTION STAGE ROUNDING OPTIONS
Outputs
The 5 MSBs for each DAC on the HSP50415 drive a
thermometer decoder , which is a digital decoder that has a
5-bit binary coded input word with 2 5 -1 (or 31) output bits,
where the number of output bits that are active correlate
directly to the input binary word. The HSP50415 uses a
RNDBITS<1:0>
00
01
10
11
ROUND SELECTION
No rounding performed, data is truncated
Round to 14-bits
Round to 12-bits
Round in both positions
thermometer decoder to significantly minimize the output
glitch energy for each DAC. I/QOUTA and I/QOUTB are
complementary current outputs. The sum of the two currents
is always equal to the full scale output current minus one
LSB. If single ended use is desired, a load resistor can be
used to convert the output current to a voltage. It is
recommended that the unused output be either grounded or
equally terminated. The voltage developed at the output
If saturation does occur, the output is symmetrically limited.
Digital to Analog (D/A) Converters
The HSP50415 outputs using dual 12-bit, 150MSPS, high
speed, low power, D/A converters. The converter provides
20mA of full scale output current and includes edge-
triggered CMOS input data latches. Low glitch energy and
excellent frequency domain performance is achieved by the
DACs segmented current source architecture.
14
must not violate the output voltage compliance range of -
0.3V to 1.25V. R LOAD (the impedance loading each current
output) should be chosen so that the desired output voltage
is produced in conjunction with the output full scale current.
If a known line impedance is to be driven, then the output
load resistor should be chosen to match this impedance.
The output voltage equation is:
V OUT = I OUT X R LOAD .
FN4559.6
April 23, 2007
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