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参数资料
| 型号： | HSP50415VIZ |
| 厂商： | Intersil |
| 文件页数： | 20/29页 |
| 文件大小： | 0K |
| 描述： | IC MODULATOR PROGRAMABLE 100MQFP |
| 标准包装： | 66 |
| 功能： | 调制器 |
| 封装/外壳： | 100-BQFP |
| 包装： | 托盘 |
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HSP50415
TABLE 15. DEVICE CONFIGURATION CONTROL (Continued)
ADDRESS = 01 H
BIT NO.
12
11:10
9:6
5
4
3
2
1
0
BIT NO.
31:24
23
22
21:20
19
18
DESCRIPTION
2-bit Filter Mode. Input data at 2x rate with ? # taps used.
Shaping Filter Interpolation
00 B = 4x
01 B = 8x
10 B = 16x
11 B = reserved
Data Bit Width NumBits/2 B12 -1
If Bit 12 = 0,
0000 B = 1 bit
0001 B = 2 bits…
1110 B = 15 bits
1111 B = 16 bits
If Bit 12 = 1,
0000 B = 2 bits
0001 B = 4 bits…
1110 B = 30 bits
1111 B = 32 bits
X/Sin(X) Filter Bypass.
0 = Enable 1 = Bypass
Half Band Filter Enable
0 = Bypass 1 = Enable
Shaping Filter Bypass
0 = Enable 1 = Bypass
Decimate by 2 at output of Shaping Filter
0 = Disable 1 = Enable
Constellation Map Bypass
0 = Enable 1 = Bypass
FIFO Bypass
0 = Enable 1 = Bypass
TABLE 16. FIFO AND I/O CONTROL
ADDRESS = 02 H
DESCRIPTION
FIFO Frequency Term 4 Loop Filter <7:0>.
FIFO Full Stop Writing
FIFO Empty, Force 0 data
FIFO Threshold Mode
00 B = Disable Threshold Logic and FIFOUnderFlow / FIFOOverFlow flags
01 B = Enable Thresholds, Disable Symbol Rate Modifications
10 B = Enable Thresholds and Modify Frequency Error Term
11 B = Enable Thresholds and Force lag accumulator to Limit
FIFO TXEN Zero Data. (Function: If FIFO Reads are gated with TXEN Pin then force data out of FIFO
block to 0x0000 if TXEN is inactive.)
FIFO TXEN Enable Gated Write
0 = TXEN Pin gates writing to FIFO
1 = FIFO writes not gated by TXEN
20
RESET STATE
0 B
00 B
0000 B
1
0
1
0
1
1
RESET STATE
00 H
0
0
00 B
0
0
FN4559.6
April 23, 2007
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