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参数资料
| 型号： | HSP50415VIZ |
| 厂商： | Intersil |
| 文件页数： | 21/29页 |
| 文件大小： | 0K |
| 描述： | IC MODULATOR PROGRAMABLE 100MQFP |
| 标准包装： | 66 |
| 功能： | 调制器 |
| 封装/外壳： | 100-BQFP |
| 包装： | 托盘 |
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HSP50415
TABLE 16. FIFO AND I/O CONTROL (Continued)
ADDRESS = 02 H
BIT NO.
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT NO.
31:24
23:14
13:4
3
2
1:0
DESCRIPTION
FIFO TXEN Gated Read
0 = FIFO reads not gated by TXEN (reads begin after 2 FIFO locations written)
1 = TXEN Pin gates read from FIFO
FIFO Underflow/Empty Pin Function
0 = Output FIFO underflow status on Pin FEMPT
1 = Output FIFO empty status on Pin FEMPT
2XSYMCLK polarity
2XSYMCLK Three-State enable
0 = off
1 = enable output
FFULL, FIFO Full Output Enable
FOVRFL, FIFO Overflow Output Enable
FEMPT, FIFO Under/Empty Output Enable
LOCKDET Output Enable
SYSCLK/2 Output Enable
INTREQ Pin Output Enable
IOUT<13:0> Output Enable
QOUT<13:0> Output Enable
TXEN Polarity
0 = Active High
1 = Active Low
ISTRB Polarity.
0 = Active High (DIN<15:0> contains Isample when ISTRB is high)
1 = Active Low (DIN<15:0> contains Isample when ISTRB is low)
SYSCLK/2 polarity.
0 = IOUT<13:0>/QOUT<15:0> data out on falling edge
1 = IOUT<13:0>/QOUT<15:0> data out on rising edge
FIFO Gated Read No Address Reset
IDAC Power Enable
QDAC Power Enable
TABLE 17. I CHANNEL CALIBRATION
ADDRESS = 03 H
DESCRIPTION
FIFO Threshold Upper Limit<7:0>
I Scale Factor<9:0>
I DC Offset <9:0>
I Negate Scale Factor
I Subtract DC Offset
I Programmable Round
00 B = No Rounding
01 B = Round to 14-bits at output
10 B = Round to 12-bits at output
11 B = Round in both positions
21
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET STATE
FF H
000 H
000 H
0
0
10 B
FN4559.6
April 23, 2007
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