参数资料
型号: HSP50415VIZ
厂商: Intersil
文件页数: 27/29页
文件大小: 0K
描述: IC MODULATOR PROGRAMABLE 100MQFP
标准包装: 66
功能: 调制器
封装/外壳: 100-BQFP
包装: 托盘
HSP50415
Electrical Specifications
VDD = +3.3V ± 5%, T A = -40°C to +85°C, Unless Otherwise Specified (Continued)
PARAMETER
DATACLK Low, t DCL
Setup Time, t DS
TEST CONDITION
DIN<15:0>, TXEN, ISTRB to DATACLK,
MIN
5
8
TYP
-
-
MAX
-
-
UNITS
ns
ns
(Note 1)
Hold Time, t DH
DIN<15:0>, TXEN, ISTRB from DATACLK,
0
-
-
ns
(Note 1)
AC CHARACTERISTICS: DIGITAL STATUS / DATA
REFCLK Frequency, f RCK
REFCLK High, t RCH
REFCLK Low, t RCL
-
5
5
-
-
-
CLK / 4
-
-
MHz
ns
ns
Digital Status and Output Data Delay, t DO
From SYSCLK/2
-
-
5
ns
Includes IOUT<13:0>, FIFO status pins,
LOCKDET and INTREQ., (Note 1)
ANALOG OUTPUT PERFORMANCE:
Resolution
12
-
-
Bits
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I OS
Offset Drift Coefficient
Full Scale Gain Error, FSE
Full Scale Gain Drift
“Best Fit” Straight Line (Note 4)
(Note 4)
(Note 4)
(Note 4)
With External Reference (Notes 3, 4)
With Internal Reference (Notes 3, 4)
With External Reference (Note 4)
-
-
-0.025
-
-10
-10
-
± 1
± 0.5
0.1
± 2
± 1
± 50
-
-
+0.025
-
+10
+10
-
LSB
LSB
% FSR
ppm
FSR/ o C
% FSR
% FSR
ppm
FSR/ o C
Full Scale Output Current, I FS
With Internal Reference (Note 4)
-
2
± 100
-
-
20
ppm
FSR/ o C
mA
Output Capacitance
Output Voltage Compliance Range
Gain Matching Between Channels
Offset Matching Between Channels
Phase Matching Between Channels
(Note 1)
(Note 1, 4)
(Note 1)
-
-1.0
-8
-
-
30
-
-
± 0.05
±0. 5
-
1.25
+8
-
-
pF
V
% FSR
% FSR
Degrees
VOLTAGE REFERENCE:
Internal Reference Voltage, V REF
-
1.23
-
V
Internal Reference Voltage Drift
(Note 1)
-
± 40
-
ppm / o C
Internal Reference Output Current Sink/Source (Note 1)
-
± 0.1
-
μ A
Capability
Reference Input Impedance
Reference Input Multiplying Bandwidth
(Note 1)
(Notes 1, 4)
-
-
1
1.4
-
-
M Ω
MHz
NOTES:
1. Parameter guaranteed by design or characterization and not production tested.
2. θ JA is measured with the component mounted on an evaluation PC board in free air.
3. Gain Error measured as the error in the ratio between the full scale output current and the current through R SET (typically 625 μ A). Ideally the
ratio should be 32.
4. See ‘Definition of DAC Specifications’ section.
27
FN4559.6
April 23, 2007
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