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参数资料
| 型号： | HSP50415VIZ |
| 厂商： | Intersil |
| 文件页数： | 5/29页 |
| 文件大小： | 0K |
| 描述： | IC MODULATOR PROGRAMABLE 100MQFP |
| 标准包装： | 66 |
| 功能： | 调制器 |
| 封装/外壳： | 100-BQFP |
| 包装： | 托盘 |
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HSP50415
Pin Descriptions
(Continued)
NAME
ICOMP1,
QCOMP1
ICOMP2,
QCOMP2
REFLO
REFIO
FSADJ
RESV
NC
TYPE
I
I
I
I
I
-
-
DESCRIPTION
Compensation Pin for use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to AVDD with
a 0.1 μ F capacitor. To minimize crosstalk, the part was designed so that these pins must be connected externally,
ideally directly under the device packaging. The voltage on these pins is used to drive the gates of the PMOS
devices that make up the current cells. Only the ICOMP1 pin is driven and therefore QCOMP1 needs to be
connected to ICOMP1, but de-coupled separately to minimize crosstalk.
Compensation Pin for Internal Bias Generation. Each pin should be individually decoupled to AGND with a 0.1 μ F
capacitor. The voltage generated at these pins represents the voltage used to supply 2.0V nominal power to the
switch drivers. This arrangement helps to minimize clock feedthrough to the current cell transistors for reduced
glitch energy and improved spectral performance.
Reference Low Select. When the internal reference is enabled, this pin serves as the precision ground reference
point for the internal voltage reference circuitry and therefore needs to have a good connection to analog ground
to enable internal 1.2V reference. To disable the internal reference circuitry this pin should be connected to AVDD.
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use
0.1 μ F cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current =
32 x V FSADJ /R SET . Where V FSADJ is the voltage at this pin. V FSADJ tracks the voltage on the REFIO pin; which
is typically 1.2V if the internal reference is used.
Reserved. These pins must be floating (not connected) for proper operation.
No Connection. Pins may be connected to GND, AGND, DGND or left floating.
Functional Description
The HSP50415 is a wideband programmable modulator that
accepts an input quadrature data stream at programmable
symbol rates of up to 25MSPS (QPSK) and outputs a
modulated quadrature data stream at the final sample rate
up to 100MHz. The allowable symbol rates depend on the
modulation type selected (QPSK, 16QAM, etc.). The input
data format is parallel with respect to the bits, but serial with
respect to the I and Q samples and may be input at a
constant symbol rate or burst in at a different rate. The
HSP50415 can symbol map the input data stream per a user
programmable look up table thus allowing any standard to
be supported. The mapped symbols are then interpolated to
the final sample rate and low-pass filtered in order to limit the
spectral occupancy of the signal. The first stage filter
coefficients are user programmable, with subsequent filter
stages having fixed coefficients. The HSP50415 then
modulates the symbol data at the final sample rate onto a
carrier signal that is tunable from 0.023Hz - 50MHz (for a
final sample rate of 100MHz) producing a quadrature signal.
The signal may then be optionally X/SIN(X) filtered to
compensate for the SIN(X)/X roll-off of the DACs. To correct
for system (or DAC induced) gain imbalances between the
In phase and Quadrature signals there is a final gain
correction stage prior to the output. The final Intermediate
Frequency (IF) digital output can be converted to differential
analog signals via the onboard 12-bit DACs or may be
optionally brought out as 14-bit digital data. The 100-pin
MQFP package provides a real digital output at 1/2 the final
sample rate.
5
System CLK Generation
The HSP50415 receives I and Q input data serially at twice the
input symbol rate. The data is converted to a parallel
quadrature data stream at the symbol rate by the Front End
Data Input Block. This data stream is upsampled to the final
output sample rate of the device (FSout). This output sample
rate (maximum rate of 100MHz) is used to clock the last stage
of the digital logic and the dual 12-bit DACs and may be
provided externally on the CLK pin or may be generated by an
internal analog PLL (APLL). When enabled, the APLL uses the
CLK pin as a reference and provides a selectable CLK
multiplier of x2, x4, x8, x16 or x32 or CLK divider of /2, /4 or /8.
An external loop filter is required to be supplied at PLLRC. The
recommend configuration is shown in Figure 1, with suggested
component values calculated as:
User Input Terms:
APLLclkdivider=APLL CLK divider programmed input
APLLvcodivider=APLL VCO divider programmed input
Fclk=CLK frequency input
Fscale=loop bandwidth divisor input
Pm=loop phase margin input (degrees)
Component calculation formulas:
C1=(Fvcogain*Icp)/(wo*wo*sqrt(kk))
C2=kk*C1
R1=1/sqrt(Fvcogain*Icp*C1*sqrt(C2/C1))
Where:
Fvcogain=231000000/APLLvcodivider
Icp=0.000353
kk=(1+(sin(Pm*pi/180)))/(1-(sin(Pm*pi/180)))
wo=2*pi*((Fclk/APLLclkdivider)/Fscale)
FN4559.6
April 23, 2007
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