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| 型号： | HW-V4SX35-VIDEO-SK-EC |
| 厂商： | Xilinx Inc |
| 文件页数： | 46/112页 |
| 文件大小： | 0K |
| 描述： | VIRTEX-4 VIDEO STARTER KIT |
| 产品变化通告： | Development Systems Discontinuation 12/Jan/2009 |
| 标准包装： | 1 |
| 系列： | Virtex®-4 |
| 类型： | DSP FPGA |
| 适用于相关产品： | Virtex?-4 SX |
| 所含物品： | 开发平台，子板，电源，闪存卡，CMOS 图像传感器和软件 |
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Chapter 4: Hardware Co-Simulation
first input port on the co-simulation block. An Outport with an index of 2 will be the
second output port on the co-simulation block.
R
?
Because Gateway blocks lack an explicit index or ordering in Simulink, these ports are
added to a run-time co-simulation block in alphabetical order. If a design contains
both Gateways and Inport/Outport blocks, the Gateway ports appear last (i.e., they
have a higher index).
Shared Register
A To Register, From Register or shared register pair can be generated and co-simulated in
FPGA hardware. Here a shared register pair is defined as a To Register block and From
Register block that specify the same name (e.g., Bar). See Figure 4-2 . In hardware, a shared
register is implemented using a synthesizable register component (for VHDL) or a module
(for Verilog).
Figure 4-2: Shared Register Pair
When a design that includes a shared register pair is compiled for hardware co-simulation,
the pair is replaced by a single register instance. Both sides of the register are attached to
user design logic ; that is, logic that originated from the original System Generator model. In
this case, control of the register is not shared between the PC and FPGA hardware since all
register ports are attached to user design logic. Compiling a shared register pair to
hardware is equivalent to compiling a System Generator Register or Delay block.
Compiling a single To Register or From Register block for hardware co-simulation results
in a different type of implementation. A single register is still created to replace the To or
From Register block. Only in this case, the register connects to both the PC and FPGA
memory map logic. The side of the register in the original model remains connected to user
design logic. The other side of the register attaches to memory map interface logic.
For designs that use hardware co-simulation, shared register pairs are typically distributed
between software and FPGA hardware. In other words, one half of the pair is implemented
in the FPGA, while the other half is simulated in software using a To or From Register
block. When data is written to a software To Register block, the hardware register is
updated to with the same data. Similarly, when data is written into the hardware register,
the same data is read by the From Register software block. A software shared register can
connect to a hardware shared register simply by specifying the name of the shared register
as it was compiled for hardware co-simulation.
Shared Memory
Compiling a shared memory block for hardware co-simulation adds an addressable block
of memory into the co-simulation memory map ( Figure 4-3 ). Shared memory blocks can be
configured with a lockable or unprotected access protection mode. This section touches on
both protection modes since they are involved during co-simulation semantics.
46
Video Starter Kit
UG217 (v1.5) October 26, 2006
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| HW-V4SX35-VIDEO-SK-UK | 功能描述:VIRTEX-4 VIDEO STARTER KIT RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:Virtex®-4 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| HW-V5GBE-DK-UNI-G | 功能描述:KIT DEV V5 LXT GIGABIT ETHERNET RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-5 LXT 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| HW-V5GBE-DK-UNI-G-J | 功能描述:KIT DEV GIGABIT ETHERNET VIRTEX5 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-5 LXT 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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| HW-V5GBE-DK-UNI-G-PROMO2 | 功能描述:KIT DEV V5 LXT GIGABIT ETHERNET RoHS:是 类别:编程器，开发系统 >> 过时/停产零件编号 系列:Virtex® 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
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