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| 型号： | HW-V4SX35-VIDEO-SK-EC |
| 厂商： | Xilinx Inc |
| 文件页数： | 47/112页 |
| 文件大小： | 0K |
| 描述： | VIRTEX-4 VIDEO STARTER KIT |
| 产品变化通告： | Development Systems Discontinuation 12/Jan/2009 |
| 标准包装： | 1 |
| 系列： | Virtex®-4 |
| 类型： | DSP FPGA |
| 适用于相关产品： | Virtex?-4 SX |
| 所含物品： | 开发平台，子板，电源，闪存卡，CMOS 图像传感器和软件 |
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Co-Simulation Communication Primitives
Figure 4-3: Shared Memory
In lockable access mode, the System Generator co-simulation hardware must acquire lock
over the shared memory object before it can access its contents. When the hardware
acquires (releases) lock of the shared memory, the memory contents are transferred to
(from) the FPGA using a high-speed data transfer.
Two images of the shared memory data are used when a lockable shared memory is co-
simulated. One memory image is stored using dual port memory in the FPGA. This image
is accessed by the System Generator hardware co-simulation design and co-simulation
memory map logic. The other image is implemented as a shared memory object on the host
PC. This software shared memory image is accessed by any software shared memory
objects used in a design.
A software process or hardware circuit that wishes to access the shared memory must first
obtain the lock. If the hardware has lock of the memory, no software objects can access the
memory contents. Likewise, if a software object controls the memory, the hardware cannot
read or write to the memory. Note that lockable hardware shared memories include
additional logic to handle the mutual exclusion.
Having two shared memory images requires synchronization between software and
hardware to ensure the images are coherent. This synchronization is accomplished by
transferring the memory image between software and hardware upon lock transfer.
System Generator performs high-speed data transfers between the host PC and FPGA.
Unprotected shared memory blocks can be written to or read from at any time during co-
simulation––the memory has no notion of mutually exclusive access. To ensure data
coherency between software and hardware, a single image of the shared memory data is
shared between hardware and software. This image is stored in the FPGA using dual port
memory that is accessible as part of the co-simulation memory map. System Generator
allows both hardware design logic and other software-based shared memory objects on the
host PC to access the shared memory data concurrently. When software shared memory
objects read or write data to the shared memory, System Generator seamlessly handles
communication with the hardware memory resource.
FIFO
A To FIFO, From FIFO, or shared FIFO pair can be generated and co-simulated in hardware.
A shared FIFO pair is defined as a To FIFO block and From FIFO block which specify the
same name (e.g., Bar) ( Figure 4-4 ).
Figure 4-4: Shared FIFO Pair
Video Starter Kit
UG217 (v1.5) October 26, 2006
47
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| HW-V4SX35-VIDEO-SK-UK | 功能描述:VIRTEX-4 VIDEO STARTER KIT RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:Virtex®-4 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| HW-V5GBE-DK-UNI-G | 功能描述:KIT DEV V5 LXT GIGABIT ETHERNET RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-5 LXT 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| HW-V5GBE-DK-UNI-G-J | 功能描述:KIT DEV GIGABIT ETHERNET VIRTEX5 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-5 LXT 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| HW-V5GBE-DK-UNI-G-PROMO1 | 功能描述:KIT DEV V5 LXT GIGABIT ETHERNET RoHS:是 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| HW-V5GBE-DK-UNI-G-PROMO2 | 功能描述:KIT DEV V5 LXT GIGABIT ETHERNET RoHS:是 类别:编程器，开发系统 >> 过时/停产零件编号 系列:Virtex® 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
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