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| 型号： | HW-V4SX35-VIDEO-SK-EC |
| 厂商： | Xilinx Inc |
| 文件页数： | 48/112页 |
| 文件大小： | 0K |
| 描述： | VIRTEX-4 VIDEO STARTER KIT |
| 产品变化通告： | Development Systems Discontinuation 12/Jan/2009 |
| 标准包装： | 1 |
| 系列： | Virtex®-4 |
| 类型： | DSP FPGA |
| 适用于相关产品： | Virtex?-4 SX |
| 所含物品： | 开发平台，子板，电源，闪存卡，CMOS 图像传感器和软件 |
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Chapter 4: Hardware Co-Simulation
R
In hardware, a shared FIFO is implemented using the FIFO Generator core. The core is
configured to use independent (asynchronous) clocks and block memory for data storage.
Shared FIFOs allow the user to safely transfer data to and from the FPGA platform in co-
simulation designs that use a free-running clock mode. Shared FIFOs can also be used to
support burst transfers during co-simulation for applications with high throughput
requirements.
When a shared FIFO pair is generated for co-simulation, a single asynchronous FIFO core
replaces the two software shared FIFO blocks. The read/write FIFO sides are attached to
user design logic (i.e., logic derived from the original System Generator model) that attached
to the From FIFO and To FIFO blocks, respectively ( Figure 4-4 ). Because both FIFO sides
attach to user logic in hardware, the PC does not share control of the FIFO with the design.
Instead, the FIFO behavior is similar to a System Generator design that includes a
traditional FIFO block.
Single shared FIFO blocks are treated differently than shared FIFO pairs. A single To FIFO
or From FIFO block is replaced by an asynchronous FIFO core when it is compiled for
hardware co-simulation. One side of the FIFO (i.e., the unused shared FIFO half in System
Generator) is connected to PC interface logic. The other side is connected to user design
logic that attached to the original To or From FIFO block. In this manner, control over the
FIFO is distributed between the PC and FPGA design.
When a To FIFO block is compiled for hardware co-simulation, the write side of the FIFO
is connected to the same logic that attached to To FIFO block in user design. The read side
of the FIFO is connected to memory map interface logic that allows the PC to read data
from the FIFO during simulation. The opposite wiring approach is used when a From FIFO
block is compiled for hardware co-simulation. In this case, the write side of the FIFO is
connected to PC interface logic, while the read side is connected to the user design logic.
The host PC writes data into the FIFO and the design logic can read data from the FIFO.
Shared FIFO pairs are typically distributed between software and FPGA hardware. In
other words, one half of the pair is implemented in the FPGA while the other half is
simulated in software using a To or From FIFO block. Together, the software and hardware
portions form a fully functional asynchronous FIFO. When a software/
hardware shared FIFO pair is co-simulated, System Generator transparently manages the
necessary transactions between the PC and FPGA hardware.
When data is written to a software To FIFO block during simulation, the same data is
written to the FIFO in hardware. The design in hardware can then retrieve this data by
reading from the FIFO. Similarly, when data is written into the hardware FIFO by design
logic, the data can be read by the From FIFO software block. Note that the empty, full, read
and write count ports on the shared FIFO blocks pessimistically reflect the state of the
hardware FIFO counterpart. A software shared FIFO can connect to a hardware shared
FIFO simply by specifying the name of the shared FIFO as it was compiled for hardware
co-simulation.
Pad
FPGA platforms often include a variety of on-board devices (e.g., external memory, analog
to digital converters, etc.) that the FPGA can communicate with. For a variety of reasons, it
may be useful to form connections to these components in your System Generator models
and to use these components during hardware co-simulation. For example, if your board
includes external memory, the user can define the control and interface logic to this
memory in the user ’s System Generator design and use the physical memory during
hardware co-simulation.
48
Video Starter Kit
UG217 (v1.5) October 26, 2006
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| HW-V4SX35-VIDEO-SK-UK | 功能描述:VIRTEX-4 VIDEO STARTER KIT RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:Virtex®-4 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| HW-V5GBE-DK-UNI-G | 功能描述:KIT DEV V5 LXT GIGABIT ETHERNET RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-5 LXT 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| HW-V5GBE-DK-UNI-G-J | 功能描述:KIT DEV GIGABIT ETHERNET VIRTEX5 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-5 LXT 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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