参数资料
型号: HW-V4SX35-VIDEO-SK-EC
厂商: Xilinx Inc
文件页数: 49/112页
文件大小: 0K
描述: VIRTEX-4 VIDEO STARTER KIT
产品变化通告: Development Systems Discontinuation 12/Jan/2009
标准包装: 1
系列: Virtex®-4
类型: DSP FPGA
适用于相关产品: Virtex?-4 SX
所含物品: 开发平台,子板,电源,闪存卡,CMOS 图像传感器和软件
R
Co-Simulation Communication Primitives
The user can interface to these types of components by including board-specific I/O pads
in the user ’s System Generator models. A board-specific I/O pad is a special port that is
wired to a specific FPGA pad when the model is compiled for hardware co-simulation.
This type of port differs from standard co-simulation ports that are controlled by a
corresponding port on a hardware co-simulation block. This means that a hardware co-
simulation run-time block does not include board-specific ports on its external interface.
A board-specific I/O pad is implemented using special non-memory mapped gateway blocks
that tell System Generator to wire the signals to the appropriate FPGA pins when the
model is compiled into hardware. To connect a System Generator signal to a board-specific
port, the user should connect the appropriate wire to the special gateway (in the same way
as is done for a traditional gateway).
The user can define non-memory mapped ports for a design using the System Generator
Board Descriptor Builder application. There are two ways to invoke this application:
1.
2.
By typing xlSBDBuilder at the MATLAB command window.
By selecting Hardware Co-Simulation->New Compilation Target…
under the Compilation submenu on the System Generator parameters dialog box.
Shared Memory Read/Write Blocks
System Generator supports burst transfers to and from the FPGA during co-simulation
using the Shared Memory Read and Write blocks ( Figure 4-5 ). These blocks provide high-
speed interfaces for lockable shared memories and shared FIFO blocks that have been
compiled for co-simulation. These blocks rely on the burst-transfer support of the co-
simulation platform to read or write the contents of an entire vector or matrix signal in a
single-hardware transaction. Both blocks are described below.
Figure 4-5: Shared Memory Read and Write Blocks
The Shared Memory Read block provides a high-speed interface for reading data from a
shared memory or FIFO in hardware. The requested data is read out of the shared memory
and into a Simulink scalar, vector, or matrix signal which is written to the block’s output
port.
The Shared Memory Write block provides a high-speed interface for writing data into a
shared memory or FIFO in hardware. The Shared Memory Write block input port should
be driven by the Simulink scalar, vector, or matrix signal containing the data you would
like written into the shared memory object. Note that the width of the input data must
match the width of the shared memory, and the total number of elements in the input must
not be bigger than the depth of the shared memory or FIFO.
The bracketed text beneath each block indicates the shared memory or FIFO with which
the block interfaces. The depth and width displays on the block indicate the size of the
shared memory. These values are updated at runtime when the block makes the
connection to the shared memory object.
Video Starter Kit
UG217 (v1.5) October 26, 2006
49
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