参数资料
型号: HW-V4SX35-VIDEO-SK-EC
厂商: Xilinx Inc
文件页数: 69/112页
文件大小: 0K
描述: VIRTEX-4 VIDEO STARTER KIT
产品变化通告: Development Systems Discontinuation 12/Jan/2009
标准包装: 1
系列: Virtex®-4
类型: DSP FPGA
适用于相关产品: Virtex?-4 SX
所含物品: 开发平台,子板,电源,闪存卡,CMOS 图像传感器和软件
R
VIODC Design
The sport_sync denotes the beginning of a data write/read transfer. Sport_sync is High the
first clock cycle of the transfer and then stays Low. A complete write cycle takes 32 clock
cycles, 16 cycles of address and 16 cycles of data. The next 32 cycles are used to read the
value of the same address that was used in the write cycle.
A new write/read cycle can be started every 32 cycles. For example:
Write cycle (sport_up): <00 xx> <01 xx> <02 xx> <03 xx> <04 xx> <05 xx> …
Read cycle (sport_dn): <xx xx> <00 xx> <01 xx> <02 xx> <03 xx> <04 xx> …
Sport_up is the serial write signal. The format for a write cycle is 16-bits of address
followed by 16-bits of data.
Note: The address must be shifted by 1 bit to the left. The data is not shifted.
In Figure 5-4 , sport_up shows a write cycle using address 0x5 and data 0xCCC5. Notice that
the address is actually 0xA.
Figure 5-4: SPort Waveform
In Figure 5-4 , waveform sport_up writes addr 0x0005, data 0xCCC5, addr 0x0006 data 5556
(actual: 0x000A,0xCCC5,0x000C,0x5556). Sport_dn reads addr 0x0004, data 0x5554, addr
0x0005, 0xCCC5 (actual 0x0008,0xAAA4,0x000A,0xCCC5) delay one extra clock cycle.
Sport_dn is the serial read signal. The format of the read cycles is 16-bits address followed
by 16-bits data.
Note: The sport_dn read begins 33 clock cycles after the corresponding sport_sync signal. The
address is shifted by one bit to the left. In Figure 5-4 , sport_dn shows a read cycle.
Note: A problem with the read cycle causes it to return the previous value instead of the newly
written value. To read the correct value, two reads are required. Since a read cycle only follows a write
cycle, the value must be written into the register twice in order to successfully read the value back.
The SPort interface implemented for the VSK Diagnostics demonstration used two 16-bit
dual-port memories with depths of 32 entries. One memory was used as a write memory
and the second was used as a read memory. New register values were written into the
address location of the write memory that corresponded to the address of the VIODC
register to be written. A counter was used to continually cycle through the 32 entries so
that the contents of the write memory was continually updated to the VIODC. The read
memory was continually updated by reads from the VIODC registers.
Video Starter Kit
UG217 (v1.5) October 26, 2006
69
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