参数资料
型号: HW-V4SX35-VIDEO-SK-EC
厂商: Xilinx Inc
文件页数: 90/112页
文件大小: 0K
描述: VIRTEX-4 VIDEO STARTER KIT
产品变化通告: Development Systems Discontinuation 12/Jan/2009
标准包装: 1
系列: Virtex®-4
类型: DSP FPGA
适用于相关产品: Virtex?-4 SX
所含物品: 开发平台,子板,电源,闪存卡,CMOS 图像传感器和软件
Chapter 6: VSK Tutorial
R
Gain and Offset Theory
Figure 6-1 illustrates the video gain and offset processing system that is applied to a video
stream.
10
11
27
10
vid_in
/
+
/
round
/
vid_out
/ 10
Offset Register
/ 16
Gain Register
ug217_ch7_01_121205
Figure 6-1: Gain and Offset
The function implements the following equation for three video channels:
Vid_out = (vid_in(channel) + offset(channel)) * gain(channel)
System Architecture
In the tutorial system, the gain and offset is implemented as a new pcore and inserted into
the VSK diagnostic/demo system. See Figure 6-2 . Gain and offset for each channel are
controlled by registers that are writeable from a MicroBlaze processor. The video input
stream and output stream are supplied by the vio_if pcore which controls the VIODC
board. The VIODC pixel clock rates are determined by the video source pixel clock, while
the MicroBlaze and video processing pcores run at 100 MHz. The video sources are
buffered in FIFOs and converted to 100 MHz streams with an accompanying pixel enable
signal.
Pcores
RS-232
MicroBlaze
vio_if
VIODC
Video
I/O
DDR
VOP
vid_gain_offset
ug217_ch7_02_121205
Figure 6-2:
Gain and Offset System Architecture
Video Stream Format
The VSK demo system assumes that video streams are packed into 33-bit fields. Packing
the various video signals into a single field simplifies routing the video channel. The model
90
Video Starter Kit
UG217 (v1.5) October 26, 2006
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