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参数资料
| 型号： | HY5TQ1G831ZNFP-S5 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.4 ns, PBGA82 |
| 封装： | FBGA-82 |
| 文件页数： | 45/75页 |
| 文件大小： | 774K |
| 代理商： | HY5TQ1G831ZNFP-S5 |
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Rev. 0.5 /Sep 2007
5
HY5TQ1G431ZNFP
HY5TQ1G831ZNFP
HY5TQ1G631ZNFP
1.
DESCRIPTION
Preliminary The HY5TQ1G431ZNFP, HY5TQ1G831ZNFP and HY5TQ1G631ZNFP are a 1,073,741,824-bit CMOS Double
Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges
of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
1.1 Device Features and Ordering Information
1.1.1 FEATURES
VDD=VDDQ=1.5V +/- 0.075V
Fully differential clock inputs (CK, /CK) operation
Differential Data Strobe (DQS, /DQS)
On chip DLL align DQ, DQS and /DQS transition with CK
transition
DM masks write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
Programmable additive latency 0, CL-1, and CL-2
supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8
Programmable burst length 4/8 with both nibble
sequential and interleave mode
BL switch on the fly
8banks
8K refresh cycles /64ms
JEDEC standard 78ball FBGA(x4/x8) , 96ball FBGA(x16)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
Auto Self Refresh supported
On Die Thermal Sensor supported ( JEDEC optional )
8 bit pre-fetch
1.1
.2 ORDERING INFORMATION
* X means Binning grade (Speed/IDD...)
Part No.
Configuration
Package
HY5TQ1G431ZNFP-X*
256M x 4
82ball FBGA
HY5TQ1G831ZNFP-X*
128M x 8
HY5TQ1G631ZNFP-X*
64M x 16
100ball FBGA
1.1
.3 OPERATING FREQUENCY-TBD
Grade
Frequency [MHz]
Remark
(CL-tRCD-tRP)
CL5
CL6
CL7 CL8 CL9 CL10
-S5
DDR3-800 5-5-5
-S6
DDR3-800 6-6-6
-G6
DDR3-1066 6-6-6
-G7
DDR3-1066 7-7-7
-G8
DDR3-1066 8-8-8
-H7
DDR3-1333 7-7-7
-H8
DDR3-1333 8-8-8
-H9
DDR3-1333 9-9-9
-P8
DDR3-1600 8-8-8
-P9
DDR3-1600 9-9-9
-P1
DDR3-1600 10-10-10
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| HY5V22(L)F(P)-5 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
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