Rev. 0.5 /Sep 2007
51
HY5TQ1G431ZNFP
HY5TQ1G831ZNFP
HY5TQ1G631ZNFP
Clock Period Jitter
during DLL locking
period
tJIT
(per, lck)
- 90
90
- 80
80
- 70
70
-60
60
ps
Cycle to Cycle Period
Jitter
tJIT(cc)
200
180
160
140
ps
Cycle to Cycle Period
Jitter during DLL
locking period
tJIT
(cc, lck)
180
160
140
120
ps
Duty Cycle jitter
tJIT
(duty)
--
-
ps
Cumulative error
across 2 cycles
tERR
(2per)
-147
147
-132
132
-118
118
-103
103
ps
Cumulative error
across 3 cycles
tERR
(3per)
-175
175
-157
157
-140
140
-122
122
ps
Cumulative error
across 4 cycles
tERR
(4per)
-194
194
-175
175
-155
155
-136
136
ps
Cumulative error
across 5 cycles
tERR
(5per)
-209
209
-188
188
-168
168
-147
147
ps
Cumulative error
across 6 cycles
tERR
(6per)
-222
222
-200
200
-177
177
-155
155
ps
Cumulative error
across 7 cycles
tERR
(7per)
-232
232
-209
209
-186
186
-163
163
ps
Cumulative error
across 8 cycles
tERR
(8per)
-241
241
-217
217
-193
193
-169
169
ps
Cumulative error
across 9 cycles
tERR
(9per)
-249
249
-224
224
-200
200
-175
175
ps
Cumulative error
across 10 cycles
tERR
(10per)
-257
257
-231
231
-205
205
-180
180
ps
Cumulative error
across 11 cycles
tERR
(11per)
-263
263
-237
237
-210
210
-184
184
ps
Cumulative error
across 12 cycles
tERR
(12per)
-269
269
-242
242
-215
215
-188
188
ps
Cumulative error
across n = 13, 14,
.....49, 50 cycles
tERR
(nper)
tERR(nper)min = ( 1 + 0.68ln(n)) * JIT(per)min
tERR(nper)max = ( 1 + 0.68ln(n)) * JIT(per)max
ps
24
Data Timing
DQS, DQS# to DQ
skew, per group, per
access
tDQSQ
-
200
-
150
-
125
-
100
ps
13
DQ output hold time
from DQS, DQS#
tQH
0.38
-
0.38
-
0.38
-
0.38
-
tCK
(avg)
13, b
DQ low-impedance
time from CK, CK#
tLZ(DQ)
- 800
400
- 600
300
- 500
250
- 450
225
ps
13, 14,
a
DQ high impedance
time from CK, CK#
tHZ(DQ)
-
400
-
300
-
250
-
225
ps
13, 14,
a
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 57 apply to Table : a
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units Notes