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| 型号： | HYB18T1G160C2F-3.7 |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.5 ns, PBGA84 |
| 封装： | GREEN, PLASTIC, TFBGA-84 |
| 文件页数： | 24/70页 |
| 文件大小： | 3996K |
| 代理商： | HYB18T1G160C2F-3.7 |
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HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.60, 2008-08
30
09262007-3YK7-BKKG
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at
V
REF.
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
TABLE 24
DC & AC Logic Input Levels
TABLE 25
Single-ended AC Input Test Conditions
Symbol Parameter
DDR2-1066
DDR2-667, DDR2-800
DDR2-533
Units
Min.
Max.
Min.
Max.
Min.
Max.
V
IH.DC
DC input logic
HIGH
V
REF + 0.125 VDDQ + 0.3
V
REF + 0.125 VDDQ + 0.3
V
REF + 0.125 VDDQ + 0.3
V
V
IL.DC
DC input LOW
–0.3
V
REF – 0.125 –0.3
V
REF – 0.125
–0.3
V
REF – 0.125
V
V
IH.AC
AC input logic
HIGH
V
REF + 0.200 –
V
REF + 0.200 VDDQ + VPEAK VREF + 0.250 VDDQ + VPEAK V
V
IL.AC
AC input LOW
–
V
REF – 0.200 VSSQ – VPEAK VREF – 0.200
V
SSQ – VPEAK VREF – 0.250
V
Symbol
Condition
Value
Unit
Notes
V
REF
Input reference voltage
0.5 ×
V
DDQ
V
1)
1) Input waveform timing is referenced to the input signal crossing through the
V
REF level (for DDR2-400 and DDR2-533) and VIH/IL.AC level
(for DDR2-667, DDR2-800 and DDR2-1066) applied to the device under test.
V
SWING.MAX
Input signal maximum peak to peak swing
1.0
V
SLEW
Input signal minimum Slew Rate
1.0
V / ns
2)3)
2) The input signal minimum Slew Rate is to be maintained over the range from
V
IH.AC.MIN to VREF for rising edges and the range from VREF to
V
IL.AC.MAX for falling edges as shown in Figure 4.
3) AC timings are referenced with input waveforms switching from
V
IL.AC to VIH.AC on the positive transitions and VIH.AC to VIL.AC on the negative
transitions.
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