参数资料
型号: HYB18T1G160C2F-3.7
厂商: QIMONDA AG
元件分类: DRAM
英文描述: 64M X 16 DDR DRAM, 0.5 ns, PBGA84
封装: GREEN, PLASTIC, TFBGA-84
文件页数: 26/70页
文件大小: 3996K
代理商: HYB18T1G160C2F-3.7
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.60, 2008-08
32
09262007-3YK7-BKKG
5.4
Output Buffer Characteristics
This chapter describes the Output Buffer Characteristics.
TABLE 27
SSTL_18 Output DC Current Drive
TABLE 28
SSTL_18 Output AC Test Conditions
Symbol
Parameter
SSTL_18
Unit
Notes
I
OH
Output Minimum Source DC Current
–13.4
mA
1)2)
1)
V
DDQ = 1.7 V; VOUT = 1.42 V. (VOUTVDDQ) / IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ – 280 mV.
2) The values of
I
OH(dc) and IOL(dc) are based on the conditions given in
1) and 3). They are used to test drive current capability to ensure V
IH.MIN.
plus a noise margin and
V
IL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
I
OL
Output Minimum Sink DC Current
13.4
mA
3)
V
DDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
Symbol
Parameter
SSTL_18
Unit
Note
V
OH
Minimum Required Output Pull-up
V
TT + 0.603
V
1)
1) SSTL_18 test load for
V
OH and VOL is different from the referenced load . The SSTL_18 test load has a 20 Ohm series resistor additionally
to the 25 Ohm termination resistor into
V
TT. The SSTL_18 definition assumes that ± 335 mV must be developed across the effectively 25
Ohm termination resistor (13.4 mA
× 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum
requirement of 603 mV swing relative to
V
TT, at the ouput device (13.4 mA × 45 Ohm = 603 mV).
V
OL
Maximum Required Output Pull-down
V
TT – 0.603
V
V
OTR
Output Timing Measurement Reference Level
0.5
× V
DDQ
V
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