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| 型号： | HYB18T1G160C2F-3.7 |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.5 ns, PBGA84 |
| 封装： | GREEN, PLASTIC, TFBGA-84 |
| 文件页数： | 34/70页 |
| 文件大小： | 3996K |
| 代理商： | HYB18T1G160C2F-3.7 |
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HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.60, 2008-08
4
09262007-3YK7-BKKG
TABLE 1
Performance Table
1.2
Description
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-
Two
CMOS
Synchronous
DRAM
device
containing
1,073,741,824 bits and internally configured as an octal bank
DRAM.
The 1-Gbit device is organized as 32 Mbit
×4 I/O ×8 banks or
16 Mbit
×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1 for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 17 bit address bus for ×4 and ×8 organised components
and a 16 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The DDR2 device operates with a 1.8 V
± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
QAG Speed Code
–1.9
–25F
–2.5
–3S
–3.7
Unit
Note
DRAM Speed Grade
DDR2
–1066F
–800D
–800E
–667D
–533C
CAS-RCD-RP latencies
7–7–7
5–5–5
6–6–6
5–5–5
4–4–4
t
CK
Max. Clock Frequency
CL3
f
CK3
–
200
MHz
CL4
f
CK4
266
MHz
CL5
f
CK5
333
400
333
266
MHz
CL6
f
CK6
400
333
–
MHz
CL7
f
CK7
533
–
400
–
MHz
Min. RAS-CAS-Delay
t
RCD
13.125
12.5
15
ns
Min. Row Precharge Time
t
RP
13.125
12.5
15
ns
Min. Row Active Time
t
RAS
40
ns
Min. Row Cycle Time
t
RC
53.125
52.5
55
ns
Precharge-All (8 banks) command
period
t
PREA
15
17.5
18
18.75
ns
1)2)
1) This
t
PREA value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to
t
RP + 1 × tCK or tnRP + 1 × nCK, depending on the speed bin,
where
t
nRP = RU{ tRP / tCK(avg) } and tRP is the value for a single bank precharge.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
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| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:60 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 线串行 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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