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参数资料
| 型号： | HYB18T1G160C2F-3.7 |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.5 ns, PBGA84 |
| 封装： | GREEN, PLASTIC, TFBGA-84 |
| 文件页数： | 53/70页 |
| 文件大小： | 3996K |
| 代理商： | HYB18T1G160C2F-3.7 |
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HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.60, 2008-08
57
09262007-3YK7-BKKG
TABLE 45
ODT AC Characteristics and Operating Conditions for DDR2–667 and DDR2–800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
ODT turn-on delay
2
n
CK
1)
1) New units, “
t
CK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800 Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “
n
CK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “
t
CK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at
T
m + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER.MIN.
t
AON
ODT turn-on
t
AC.MIN
t
AC.MAX +0.7
ns
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
AOND, which is interpreted differently per speed bin. For DDR2-667/800 tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
t
AONPD
ODT turn-on (Power-Down Modes)
t
AC.MIN +2
2
t
CK + tAC.MAX +1
ns
t
AOFD
ODT turn-off delay
2.5
n
CK
t
AOF
ODT turn-off
t
AC.MIN
t
AC.MAX +0.6
ns
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK.AVG = 3 ns is assumed,
t
AOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by
counting the actual input clock edges.
t
AOFPD
ODT turn-off (Power-Down Modes)
t
AC.MIN + 2
2.5
t
CK + tAC.MAX +1
ns
t
ANPD
ODT to Power Down Mode Entry Latency
3
—
n
CK
t
AXPD
ODT Power Down Exit Latency
8
—
n
CK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
| HYB18T1G400AF-5 | 制造商:Infineon Technologies AG 功能描述:256M X 4 DDR DRAM, 0.6 ns, PBGA68 |
| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:60 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 线串行 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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