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参数资料
| 型号： | HYB18T1G160C2F-3.7 |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.5 ns, PBGA84 |
| 封装： | GREEN, PLASTIC, TFBGA-84 |
| 文件页数： | 40/70页 |
| 文件大小： | 3996K |
| 代理商： | HYB18T1G160C2F-3.7 |
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HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
Internet Data Sheet
Rev. 1.60, 2008-08
45
09262007-3YK7-BKKG
1)
V
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. DQS RDQS
5) Inputs are not recognized as valid until
V
REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is
V
TT.
7) New units, ‘
t
CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
MRS command to ODT update delay
t
MOD
0
12
0
12
ns
Mode register set command cycle
time
t
MRD
2—
2
—
nCK
OCD drive mode output delay
t
OIT
0
12
0
12
ns
DQ/DQS output hold time from DQS
t
QH
t
HP – tQHS
—
t
HP – tQHS
—ps
DQ hold skew factor
t
QHS
—
300
—
340
ps
Average periodic refresh Interval
t
REFI
—7.8
—
7.8
μs
—3.9
—
3.9
μs
Auto-Refresh to Active/Auto-Refresh
command period
t
RFC
127.5
—
127.5
—
ns
Read preamble
t
RPRE
0.9
1.1
0.9
1.1
t
CK.AVG
Read postamble
t
RPST
0.4
0.6
0.4
0.6
t
CK.AVG
Active to active command period for
1KB page size products
t
RRD
7.5
—
7.5
—
ns
Active to active command period for
2KB page size products
t
RRD
10
—
10
—
ns
Internal Read to Precharge command
delay
t
RTP
7.5
—
7.5
—
ns
Write preamble
t
WPRE
0.35
—
0.35
—
t
CK.AVG
Write postamble
t
WPST
0.4
0.6
0.4
0.6
t
CK.AVG
Write recovery time
t
WR
15
—
15
—
ns
Internal write to read command delay
t
WTR
7.5
—
7.5
—
ns
Exit active power down to read
command
t
XARD
2—
2
—
nCK
Exit active power down to read
command (slow exit, lower power)
t
XARDS
8 – AL
—
7 – AL
—
nCK
Exit precharge power-down to any
command
t
XP
2—
2
—
nCK
Exit self-refresh to a non-read
command
t
XSNR
t
RFC +10
—
t
RFC +10
—
ns
Exit self-refresh to read command
t
XSRD
200
—
200
—
nCK
Write command to DQS associated
clock edges
WL
RL – 1
RL–1
nCK
Parameter
Symbol
DDR2–800
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Min.
Max.
Min.
Max.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
| HYB18T1G400AF-5 | 制造商:Infineon Technologies AG 功能描述:256M X 4 DDR DRAM, 0.6 ns, PBGA68 |
| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:60 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 线串行 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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