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参数资料
型号： HYS72T128000EU-2.5-C2
厂商： QIMONDA AG
元件分类： DRAM
英文描述： 128M X 72 DDR DRAM MODULE, 0.4 ns, DMA240
封装： GREEN, UDIMM-240
文件页数： 9/59页
文件大小： 3071K
代理商： HYS72T128000EU-2.5-C2
HYS[64/72]T[128/256]0x0EU–[19F/1.9/25F/2.5/3S]–C2
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.00, 2008-06
17
12032007-I9KE-FFWO
3.3
Speed Grade Definitions
TABLE 12
Speed Grade Definition
TABLE 13
Speed Grade Definition
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is
V
TT.
5)
t
RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Speed Grade
DDR2–1066E
DDR2–1066F
DDR2–800D
DDR2–800E
Unit
Note
QAG Sort Name
–19F
–1.9
–25F
–2.5
CAS-RCD-RP latencies
6–6–6
7–7–7
5–5–5
6–6–6
t
CK
Parameter
Symbol Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
—
Clock Period
@ CL = 3
t
CK
––––585
8ns
1)2)3)4)
@ CL = 4
t
CK
3
7.5
3.75
7.5
3.75
8
3.75
8
ns
1)2)3)4)
@ CL = 5
t
CK
2.57.5
3
7.5
2.58
3
8
ns
1)2)3)4)
@ CL = 6
t
CK
1.875
7.5
1.875
7.5
2.5
8
2.5
8
ns
1)2)3)4)
@ CL = 7
t
CK
1.875
7.5
1.875
7.5
2.5
8
2.5
8
ns
1)2)3)4)5)
Row Active Time
t
RAS
45
70k
45
70k
45
70k
45
70k
ns
1)2)3)4)5)
Row Cycle Time
t
RC
56.25
–
58.125 –
57.5
—
60
—
ns
1)2)3)4)
RAS-CAS-Delay
t
RCD
11.25
–
13.125 –
12.5
—
15
—
ns
1)2)3)4)
Row Precharge Time
t
RP
11.25
–
13.125 –
12.5
—
15
—
ns
1)2)3)4)
Speed Grade
DDR2–667D
Unit
Note
QAG Sort Name
–3S
CAS-RCD-RP latencies
5–5–5
t
CK
Parameter
Symbol
Min.
Max.
—
Clock Period
@ CL = 3
t
CK
58ns
1)2)3)4)
@ CL = 4
t
CK
3.75
8
ns
1)2)3)4)
@ CL = 5
t
CK
38ns
1)2)3)4)
Row Active Time
t
RAS
45
70k
ns
1)2)3)4)5)
Row Cycle Time
t
RC
60
—
ns
1)2)3)4)
RAS-CAS-Delay
t
RCD
15
—
ns
1)2)3)4)
Row Precharge Time
t
RP
15
—
ns
1)2)3)4)
相关PDF资料
PDF描述
HYS72T64000EP-3.7-B2 64M X 72 DDR DRAM MODULE, DMA240
HZ20-1 19.25 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35
HZ6B1L 5.65 V, 0.4 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35
HZ9.1CP 9.65 V, 1 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-41
HZB6.8MWA 6.8 V, 0.2 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE
相关代理商/技术参数
参数描述
HYS72T128000GR 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
HYS72T128000GR-37-A 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
HYS72T128000GR-5-A 制造商:INFINEON 制造商全称:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
HYS72T128000HP 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128000HP-2.5-B 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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