参数资料
型号: IBM25PPC750CX-CP40-3T
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256
封装: PLASTIC, BGA-256
文件页数: 24/43页
文件大小: 509K
代理商: IBM25PPC750CX-CP40-3T
PowerPC 750CX RISC Microprocessor Datasheet
Page 30
Version 1.2
Jun 20, 2001
Table 14: PowerPC 750CX Microprocessor PLL Conguration
PLL_CFG
(0:3)
Processor to
Bus Frequency
Ratio
(r)
Frequency Range Supported by VCO having an example range of
VCO
MIN = 500 to VCOMAX = 1GHz
6
SYSCLK
Core
bin
dec
Min
Max
Min
Max
0000
0
2.5x
120
1335
300
333
0001
1
7.5x
40
67
300
5006
0010
2
7x
43
71
0011
3
PLL Bypass3
N/A
0100
4
2x
Note 1
0101
5
6.5x
46
77
300
5006
0110
6
10x
50
310
5006
0111
7
4.5x
66
111
300
5006
1000
8
3x
100
1335
1001
9
5.5x
55
109
1010
10
4x
75
150
1011
11
5x
40
120
1100
12
8x
37
75
1101
13
6x
50
100
1110
14
3.5x
85
172
1111
15
Off4
N/A
Off
Note:
1. The 2X Processor to Bus Ratio is currently not supported.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see section “Clock AC Specifications” on page 14 for
valid SYSCLK and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for
1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply
in PLL-bypass mode.
4. In Clock - off mode, no clocking occurs inside the PowerPC 750CX regardless of the SYSCLK input.
5. The SYSCLK limit is 133MHz, as specified in Table 6 on page 15. Applications requiring SYSCLK over 133MHz will be investigated by
application conditions.
6. VCO
MAX is specified in this table by the maximum core processor speed. The VCO maximum of 1GHz reflects a processor core speed of
500MHz.
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