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| 型号： | IBM25PPC750CX-CP40-3T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 7/43页 |
| 文件大小： | 509K |
| 代理商： | IBM25PPC750CX-CP40-3T |
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PowerPC 750CX RISC Microprocessor Datasheet
Jun 20, 2001
Version 1.2
Page 15
Figure 2. SYSCLK Input Timing Diagram
Table 6: Clock AC Timing Specications1,6
See Table 2 on page 12, for recommended operating conditions.
Num
Characteristic
Value
Unit
Notes
Min
Max
Processor frequency
300
500
MHz
6
SYSCLK frequency
31
133
MHz
1
SYSCLK cycle time
7.5
32
ns
2,3
SYSCLK rise and fall time (slew rate)
1.0
2.0
volt/ns
2,3
4
SYSCLK duty cycle measured at 0.8V
25
75
%
3
SYSCLK jitter
–
±150
ps
4,3
Internal PLL relock time
–
100
s5
Note:
1. Caution: The SYSCLK frequency and the PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) fre-
quency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal
description in Section “PLL Configuration,” on page 28 for valid PLL_CFG[0-3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 to 1.2V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±150ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock
after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time
during the power-on reset sequence.
6. For applications with processor frequencies below 300MHz, application conditions need to be investigated.
VM
CV
IL
CV
IH
1
2
4
3
4
SYSCLK
VM - Midpoint Voltage (0.8V)
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