- 您现在的位置：买卖IC网 > PDF目录67683 > IBM25PPC750CX-CP40-3T 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 PDF资料下载
参数资料
| 型号： | IBM25PPC750CX-CP40-3T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 9/43页 |
| 文件大小： | 509K |
| 代理商： | IBM25PPC750CX-CP40-3T |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页
PowerPC 750CX RISC Microprocessor Datasheet
Jun 20, 2001
Version 1.2
Page 17
Figure 4 provides the mode select input timing diagram for the PowerPC 750CX.
5.4
60X Bus Output AC Specications
Table 8 provides the 60X bus output AC timing specications for the PowerPC 750CX as dened in Figure 6 on
Figure 4. Mode Select Input Timing Diagram
Table 8: 60X Bus Output AC Timing Specications1,4,6,7
See Table 2 on page 12 for operating conditions.
Num
Characteristic
1.8V Mode
2.5V Mode
Unit
Notes
Min.
Max.
Min.
Max.
12
SYSCLK to Output Driven (Output Enable Time)
0.3
ns
13
SYSCLK to Output Valid
–
2.31
–
2.61
ns
14
SYSCLK to Output Invalid (Output Hold)
0.400
ns
2
15
SYSCLK to Output High Impedance (all signals except ARTRY)
–
2.5
–
2.5
ns
16
SYSCLK to ARTRY high impedance before precharge
–
3.0
–
3.0
ns
17
SYSCLK to ARTRY precharge enable
0.2
t
SYSCLK
+ 1.0
0.2
t
SYSCLK
+ 1.0
ns
2, 3, 5
18
Maximum delay to ARTRY precharge
1
t
SYSCLK
3, 5
19
SYSCLK to ARTRY high impedance after precharge
2
t
SYSCLK
3, 5
Note:
1. All output specifications are measured from the midpoint voltage (0.8V) of the rising edge of SYSCLK to the midpoint voltage of the signal in question
defined in figure 5. Both input and output timings are measured at the pin. Timings are determined by design.
2. This minimum parameter assumes CL = 0pF.
3. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration of the parameter in question.
4. Output signal transitions are defined in figure 5.
5. Nominal precharge width for ARTRY is 1.0 tSYSCLK.
6. Guaranteed by design and characterization, and not tested.
7. These timings are valid for processors up to 466MHz. 500MHz processor timing behavior and characterization are being evaluated at this time.
VIH
V
IH = 1.24V
MODE PINS
10c
11b
HRESET
10c
11b
相关PDF资料 |
PDF描述 |
|---|---|
| IBM25PPC750CXEFP10-3T | RISC PROCESSOR, PBGA256 |
| IBM25PPC750CXEJP7012T | 32-BIT, 600 MHz, RISC PROCESSOR, PBGA256 |
| IBM25PPC750CXEJP5523T | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA256 |
| IBM25PPC750CXEJQ5012T | 32-BIT, 500 MHz, RISC PROCESSOR, PBGA256 |
| IBM25PPC750CXEJQ4012T | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IBM25PPC750CXEJP2013T | 制造商:IBM Microelectronics 功能描述:MPU 750XX RISC 32BIT 0.18UM 400MHZ 1.8V/2.5V 256BGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC750CXEJP2013T Co-Processors |
| IBM25PPC750CXEJP5512T | 制造商:IBM 功能描述: |
| IBM25PPC750CXEJP7012T | 制造商:IBM Microelectronics 功能描述:MPU 750XX RISC 32BIT 0.18UM 600MHZ 1.8V/2.5V 256BGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC750CXEJP7012T Co-Processors |
| IBM25PPC750CXEJP7013T | 制造商:IBM 功能描述:IBMIBM25PPC750CXEJP7013T OEM EOL151207 |
| IBM25PPC750FL-GR0123V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
发布紧急采购，3分钟左右您将得到回复。