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参数资料
| 型号： | IBM25PPC750CX-CP40-3T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 43/43页 |
| 文件大小： | 509K |
| 代理商： | IBM25PPC750CX-CP40-3T |
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PowerPC 750CX RISC Microprocessor Datasheet
Jun 20, 2001
Version 1.2
Page 9
3.0 Features
This section summarizes the features of the PowerPC 750CX’s implementation of the PowerPC architecture. Major fea-
tures of the PowerPC 750CX are as follows.
Branch processing unit
- Four instructions fetched per clock
- One branch processed per cycle (plus resolving 2 speculations)
- Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
- 512-entry branch history table (BHT) for dynamic prediction
- 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay slots
Dispatch unit
- Full hardware detection of dependencies (resolved in the execution units)
- Dispatch two instructions to six independent units (system, branch, load/store, xed-point unit 1, xed-point
unit 2, or oating-point)
- 4-stage pipeline: fetch, dispatch, execute, and complete
- Serialization control (predispatch, postdispatch, execution, serialization)
Decode
- Register le access
- Forwarding control
- Partial instruction decode
Load/store unit
- One cycle load or store cache access (byte, half-word, word, double-word)
- Effective address generation
- Hits under misses (one outstanding miss)
- Single-cycle misaligned access within double word boundary
- Alignment, zero padding, sign extend for integer register le
- Floating-point internal format conversion (alignment, normalization)
- Sequencing for load/store multiples and string operations
- Store gathering
- Cache and TLB instructions
- Big and little-endian byte addressing supported
- Misaligned little-endian support in hardware
Fixed-point units
- Fixed-point unit 1 (FXU1); multiply, divide, shift, rotate, arithmetic, logical
- Fixed-point unit 2 (FXU2); shift, rotate, arithmetic, logical
- Single-cycle arithmetic, shift, rotate, logical
- Multiply and divide support (multi-cycle)
- Early out multiply
- Thirty-two, 32-bit general purpose registers
- Secondary FXU executes integer add/compare instructions
Floating-point unit
- Support for IEEE-754 standard single and double-precision oating-point arithmetic
- Optimized for single-precision multiply/add
- Thirty-two, 64-bit oating point registers
- Enhanced reciprocal estimates
- 3-cycle latency, 1-cycle throughput, single-precision multiply-add
- 3-cycle latency, 1-cycle throughput, double-precision add
- 4-cycle latency, 2-cycle throughput, double-precision multiply-add
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| IBM25PPC750CXEJP7012T | 32-BIT, 600 MHz, RISC PROCESSOR, PBGA256 |
| IBM25PPC750CXEJP5523T | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA256 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IBM25PPC750CXEJP2013T | 制造商:IBM Microelectronics 功能描述:MPU 750XX RISC 32BIT 0.18UM 400MHZ 1.8V/2.5V 256BGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC750CXEJP2013T Co-Processors |
| IBM25PPC750CXEJP5512T | 制造商:IBM 功能描述: |
| IBM25PPC750CXEJP7012T | 制造商:IBM Microelectronics 功能描述:MPU 750XX RISC 32BIT 0.18UM 600MHZ 1.8V/2.5V 256BGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC750CXEJP7012T Co-Processors |
| IBM25PPC750CXEJP7013T | 制造商:IBM 功能描述:IBMIBM25PPC750CXEJP7013T OEM EOL151207 |
| IBM25PPC750FL-GR0123V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
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