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| 型号： | IBM25PPC750CX-CP40-3T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 32/43页 |
| 文件大小： | 509K |
| 代理商： | IBM25PPC750CX-CP40-3T |
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PowerPC 750CX RISC Microprocessor Datasheet
Page 38
Version 1.2
Jun 20, 2001
7.9
Operational and Design Considerations
7.9.1 Level Protection
A level protection feature is included in the PowerPC 750CX RISC Microprocessor in releases DD2.0 and later. The
level protection feature is available only in the 1.8V bus mode. This feature prevents ambiguous oating reference volt-
ages by pulling the respective signal line to the last valid or nearest valid state.
For example, if the I/O voltage level is closer to OV
DD, the circuit pulls the I/O level to OVDD; if the I/O level is closer to
GND, the I/O level is pulled low. This self-latching circuitry “keeps” the oating inputs dened and avoids meta-stabil-
ity. In Table 16, these signals are dened as “keeper” in the "Level Protect" column.
The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of current
must be applied to the “keeper” node to overcome the level protection latch. This current is process dependent, but in no
case is the current required over 100
A.
This feature allows the system designer to limit the number of resistors in the design and optimize placement and reduce
costs.
7.9.2 64 or 32-Bit Data Bus Mode
Typical operation is considered to be in 64-bit Data Bus mode. Mode setting is determined by the state of the mode sig-
nal (QACK) at the transition of HRESET from its active to inactive state (low to high). If QACK is low when HRESET
transitions from active to inactive, 64-bit mode is selected. If QACK is high when HRESET transitions from active to
inactive, 32-bit mode is selected.
7.9.3 1.8V and 2.5V I/O Signal Support
Selection between 1.8V and 2.5V I/O is accomplished using the BVSEL pin. If BVSEL is set low then the 1.8V mode is
enabled. If BVSEL is set high, then the 2.5V mode is enabled. Due to bus timings restrictions, only uniprocessor imple-
mentations are recommended. No multiprocessor support is advised.
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相关代理商/技术参数 |
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|---|---|
| IBM25PPC750CXEJP2013T | 制造商:IBM Microelectronics 功能描述:MPU 750XX RISC 32BIT 0.18UM 400MHZ 1.8V/2.5V 256BGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC750CXEJP2013T Co-Processors |
| IBM25PPC750CXEJP5512T | 制造商:IBM 功能描述: |
| IBM25PPC750CXEJP7012T | 制造商:IBM Microelectronics 功能描述:MPU 750XX RISC 32BIT 0.18UM 600MHZ 1.8V/2.5V 256BGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC750CXEJP7012T Co-Processors |
| IBM25PPC750CXEJP7013T | 制造商:IBM 功能描述:IBMIBM25PPC750CXEJP7013T OEM EOL151207 |
| IBM25PPC750FL-GR0123V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
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