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参数资料
| 型号： | IBM25PPC750CX-CP40-3T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 28/43页 |
| 文件大小： | 509K |
| 代理商： | IBM25PPC750CX-CP40-3T |
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Jun
20,
2001
Version
1.2
PowerPC
750CX
RISC
Microprocessor
Datasheet
Page
34
Table 16: Input-Output Usage
PowerPC 750CX
Signal Name
Active
Level
Input/
Output
Usage Group
I/O with Internal
Resistors
Level Protect
Required External
Resistor
Comments
A0-31
N/A
BIDI
Address Bus
Keeper
See Note 1
AACK
Low
IN
Address Termination
Keeper
Has to be actively driven
ARTRY
Low
BIDI
Address Termination
Keeper
Resistor by design
Needs pullup DD2.0 also
BG
Low
IN
Address Arbitration
Keeper
Active driver or pulldown
BR
Low
OUT
Address Arbitration
Keeper
Chip actively drives
BVSEL
N/A
IN
I/O Level
Keeper
5K DD1.0, 2.0, 2.1, 2.2 Sel high or low as design
CI
Low
OUT
Transfer Attributes
Keeper
See Note 1
CKSTP_IN
Low
IN
Interrupt/Resets
Keeper
Has to be actively driven
CKSTP_OUT
Low
OUT
Interrupt/Resets
Keeper
No requirement
DBG
Low
IN
Data Arbitration
Keeper
Active driver or tie low
DH0-31
N/A
BIDI
Data Bus
Keeper
See Note 1
DL0-31
N/A
BIDI
Data Bus
Keeper
See Note 1
GBL
Low
BIDI
Transfer Attributes
Keeper
See Note 1
HRESET
Low
IN
Interrupt/Resets
Keeper
Active driver and see Note 2.
INT
Low
IN
Interrupt/Resets
Keeper
Active driver or pullup
L1_TSTCLK
N/A
IN
LSSD
Not enabled
5K DD1.0, 2.0, 2.1, 2.2 Pullup required
L2_TSTCLK/
DBWO
Low
IN
LSSD
Not enabled
5K DD1.0, 2.0, 2.1, 2.2 Pullup required
LSSD_MODE
Low
IN
LSSD
Not enabled
5K DD1.0, 2.0, 2.1, 2.2 Pullup required
MCP
Low
IN
Interrupt/Resets
Keeper
Active driver or pullup
PLL_CFG (0-3)
N/A
IN
Clock Control
Keeper
As required
Pullup/pulldown, as required
QACK
Low
IN
Status/Control
Keeper
Has to be actively driven
QREQ
Low
OUT
Status/Control
Keeper
Chip actively drives
SRESET
Low
IN
Interrupt/Resets
Keeper
Active driver or pullup, see Note 2.
Note:
1. Depends on the system design
2. HRESET, SRESET, and TRST are signals used for ESP and RISCWatch to enable proper operation of the debuggers. Logical AND gates should be placed between these signals and PowerPC 750CX
RISC Microprocessor. (Refer to Figure 17 on page 36.)
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