Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
Dimensions and Signal Assignments
750GX_ds_body.fm SA14-2765-02
September 2, 2005
Table 4-3. Signal Listing for the CBGA Package
Signal Name
Pin Count
Active
Input/Output
Notes
A[0:31]
32
High
Input/Output
A1VDD
1
—
Supply for PLL0
A2VDD
1
—
Supply for PLL1
AACK
1
Low
Input
ABB
1
Low
Input/Output
AGND
1
—
Ground for PLL
AP[0:3]
4
High
Input/Output
ARTRY
1
Low
Input/Output
BG
1
Low
Input
BR
1
Low
Output
BVSEL
1
High
Input
I/O voltage mode select for 60x bus.
CI
1
Low
Output
CKSTP_IN
1
Low
Input
CKSTP_OUT
1
Low
Output
CLK_OUT
1
High
Output
DBB
1
Low
Input/Output
DBDIS
1
Low
Input
Factory usage mode pin. Pull inactive (high) when
HRESET transitions from low to high for normal
machine operation.
DBG
1
Low
Input
DBWO
1
Low
Input
Factory usage mode pin. Pull inactive (high) when
HRESET transitions from low to high for normal
machine operation.
DH[0:31]
32
High
Input/Output
DL[0:31]
32
High
Input/Output
DP[0:31]
8
High
Input/Output
DRTRY
1
Low
Input
Optional data retry mode select. This function will be
set when HRESET transitions from low to high.
DRTRY high indicates data-retry mode; DRTRY low
indicates no data-retry mode.
GBL
1
Low
Input/Output
Ground
60
—
Common ground
HRESET
1
Low
Input
Notes:
1. QACK in a logical high state at the transition of HRESET from asserted to negated enables standard pre-charge mode in the
750GX.
QACK in a logical low state at the transition of HRESET from asserted to negated enables extended pre-charge mode in the
750GX.
2. QACK, in a logical low state at the transition of QREQ from asserted to negated, enables the 750GX processor to enter the soft
stop (Nap) state for proper JTAG emulator operation.