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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 10/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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18
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
72 Bit Lookup
71
0
Available for 2 Clk2x Cycles
144 Bit Lookup
143
72 71
0
Available in 1st Clk2x Cycle
Available in 2nd Clk2x Cycle
Address
0 X 0
0 X 1
288 Bit Lookup
287
216 215
144 143
72 71
0
1st Clk2x
2nd Clk2x
3rd Clk2x
4th Clk2x
Address
0 X 0
0 X 1
0 X 2
0 X 3
E5325 tbl 05
Figure 3.1 Request Bus for Lookup Commands
Figure 3.2 Format of Address for Request Bus
INSTRUCTION TYPE
71
34 33
26 25
24 23
22
21
20
17
16
15
14
1
0
Read & Writes
of Data and
Mask
Reserved(1)
Device ID
Access
Type
GMR
Select
0:Direct
1:Indirect
SRR
Select
A14
A13(2)
Address
A13(2)
A0
Reserved
(1)
71
34 33
26 25
24 23
8 7
0
Read & Writes
of Registers
Reserved(1)
Device ID
Access
Type
Reserved(1)
Register Address
71
34 33
26 25
24 23
21 20
16
15
14
0
SRAM Read,
Write and No
Wait Read
Reserved(1)
Device ID
Access
Type
Reserved(1)
Address
A19
A15
A14(3)
Address
A14(3)
A0
E5325 tbl 06a
Request Bus Format
Request Bus
TheRequestBusisa72-bitbus.Oneofitstwomainfuncitionsistosupply
the data for the Lookup command. The order of the data supplied for a
72-bit, 144-bit and 288-bit Lookup commands is specified in Figure 3.1.
NOTES:
1. Reserved bits should be set to "0's".
2. For Read and Write commands of Data, Mask and Registers, Address 13 must be driven on Bit 14 and Bit 15.
3. For SRAM Write, SRAM Read and SRAM No Wait Read commands, Address 14 must be driven on Bit 14 and Bit 15.
For all other Read and Write Commands, the Request Bus is used to
specify the address followed by the relevant data.
The Address format is shown below in Figure 3.2 and the data is
presented as shown in the above Figure 3.1. For wider width entries
(x144 and x288) the Data order with its respective address is also shown.
For Read and Write commands of the Data cells, Mask cells and
Registers. The format of the Request Bus is illustrated in the top part of
Figure 3.2. Each of the fields are described on the next page.
For SRAM Read, SRAM Write and SRAM No Wait Read commands,
theformatoftheRequestBusisillustratedinthebottompartofFigure3.2.
Note:Forallcommands,theSAMEADDRESSmustbedrivenonRequest
Bus Bit 14 and Request Bus Bit 15.
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