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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 31/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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6.42
37
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
SRAM No Wait Read (PBSRAM)
Sequence Diagrams
NOTES:
1
.
CCLK
is
an
internal
signal
not
seen
by
the
user.
2
.
The
SRAM
No
Wait
Read
command
does
not
require
the
user
to
wait
until
the
Read
is
complete.
If
the
next
command
is
a
SRAM
Wri
te,
it
can
be
initiated
during
the
cycle
t6
.
Two
dead
cycles
are
inserted
to
insure
that
no
contention
occurs
on
the
SRAM
Data
Bus.
All
other
commands
can
be
initiated
on
the
cycle
t
2.
3
.
The
Index
Bus
is
driven,
but
to
an
indeterminate
state.
4
.
For
Synchronous
Pipeline
Burst
SRAM,
the
CE
input
is
tied
Low,
ADSP
is
tied
HIGH,
ADSC
is
tied
LOW,
and
the
OE
input
is
driven
by
the
IPC
CE
/OE
output.
5.
HITACK
and
VALID
signals
can
be
valid
based
on
the
rising
edge
of
CLK2X
at
time
tCDV
dependent
on
the
Pipeline
Delay
(PD)
v
alue
that
is
programmed
into
the
System
Configuration
Register
(SCR).
These
signals
will
drive
for
2
CLK2X
cycles.
A
PD
value
of
2
is
shown.
Refer
to
Output
Timing
(with
ZBT
SRAM)
for
the
relative
timing
of
all
PD
values.
INDE
X
SR
A
M
R
EAD
D
A
T
A
RE
Q
D
A
T
A
I5325
d
rw
1
IND
X
MA
T
C
H
O
UT
O
E
(4
)
SR
A
M
D
A
T
A
HIT
A
CK
(5
)
VA
L
ID
(5
)
CM
D[6:
4]
W
E
RDA
CK
R
EAD
AD
D
R
ESS
A
DDRE
S
O
R
DA
T
A
F
O
R
N
E
X
T
CO
M
A
ND
CLK2X
CC
L
K
(1
)
CM
D[3:0]
t 1
t 2
t 3
t 4
t 5
t 6
t 7
t 8
t 0
t 9
t 10
t 11
t 12
t 13
t 14
t 15
t 16
RE
Q
S
TB
N
e
x
t
c
o
m
and
c
a
n
b
e
ini
ti
at
ed
th
is
c
y
c
le.
(S
ee
not
e
2
)
(S
R
A
M
N
o
W
a
it
R
ead
)
S
R
AM
AC
C
E
SS
CO
M
A
ND
NE
X
T
C
O
M
A
N
D
NO
T
E
3
NO
T
E
3
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