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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 23/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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6.42
3
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
x
System Configurations and Functional Highlights
x
Signal Descriptions and Pinout
x
DC Operating Characteristics
x
RegisterDescription
- ConfigurationRegisters
- Reply Width Registers (RWRs)
- Search Result Registers (SRRs)
- Global Mask Registers (GMRs)
x
BusDescription
- Command Bus Format
- GMR and SRR Select
- Request Bus Format
- Index Bus Format
- AdditionalSignals
x
Initialization
x
AC Operating Characteristics
x
TimingDiagrams
x
Sequence Diagrams
x
JTAGInterfaceSpecifications
x
Package Diagram Outline
x
OrderingInformation
Functional Highlights
System Configurations and Functional Highlights
Figure 1.1
System Configurations
Figure 1.0A ASIC / IP Co-Processor / SRAM configuration
Figure 1.0B - ASIC / IP Co-Processor configuration
Bus Interface
The IP Co-Processor utilizes a dual bus interface consisting of the
Request Bus and the Index Bus.
The72bitbi-directionalRequestBusfunctionsasamultiplexedaddress
and data bus, which performs the writing and reading of IP Co-Processor
resources, as well as presenting lookup data to the device.
The Index Bus is an independent unidirectional bus which drives the
result of the lookup (or index) to either an SRAM device or an ASIC. In
addition to driving the Index, the IPC also drives the associated SRAM
control signals (
CE/OE, and WE) for either ZBT or Synchronous
Pipeline Burst SRAM devices.
Readingdata,maskorregisterentrieswillalwaysresultin72bitsofdata
driven on the Request Bus. Writes will also be 72 bits of data.
Data and Mask Array
The IDT75T43100 has 32K x 72 Data cell
entries and 32K x 72 associated Mask cell
entries as shown in Fig. 1.1. This combination
of Data and Mask cell entries enables the
IDT75T43100 to store 0, 1 or X, making it a full
ternary array IP Co-Processor. During a
lookup operation, both arrays are used along
with a Global Mask Register to find a match to
a requested data word.
The IDT75T43100 is designed to fulfill the needs of various types of
Networking systems. In solutions requiring data searching such as
routers, a network interface as shown in Fig 1.0A may be realized. Here
the IDT IP Co-Processor (IPC) interfaces directly to an ASIC/ FPGA for
lookupsandroutesanindextoanassociatedSRAMdevice,thatsupplies
the next hop address via an SRAM Data Bus to the ASIC. The IPC also
provides the required control signals to directly hookup to ZBT or
Synchronous Pipeline Burst SRAM.
IDT’s IPC can also be configured without using the SRAM interface
as shown in Fig. 1.0B Here the IDT75T43100 processes the lookups
submittedbythecontrollerandfeedstheresultdirectlybacktotheASIC/
FPGA.Inthismanner, thefullcapabilitiesoftheIPCarefullyutilizedwithout
requiring the use of an external SRAM.
The IPC provides the user control of the associated handshake
signals to adapt to either configuration.
Command Bus
TheIDT75T43100carriesa 7-bitCommandBus,whichloadsspecific
instructionsintotheIPCo-Processor.Theseinclude:
x
Read or Write
A Read or Write instruction placed on the Command Bus operates on
a specified data entry, mask entry, or register. During the initiation of a
Read command, the Request Bus will be driven with an address, a fixed
numberofclockcycleslaterthissamebuswillbedrivenwith therespective
databack. DuringtheinitiationofaWritecommand,theRequestBuswill
receive the address during the 1st cycle followed by the respective data
on the 2nd cycle. All reads and writes are 72-bit entities.
Datasheet Features
A5325 drw 03
32K x 72
Da ta
Mask
A5325 drw02a
ASIC
or
FPGA
Network
Interface
IDT
IP Co-Processor
Sync
or
ZBT SRAM
A 5 325 drw 0 2b
Network
Interface
ASIC
or
FPGA
IDT
IP Co-Processor
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