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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 29/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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6.42
35
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
SRAM Read (PBSRAM)
Sequence Diagrams
NOTES:
1
.
CCLK
is
an
internal
signal
not
seen
by
the
user.
2
.
Commands
initiated
from
t
2to
t
12
are
ignored.
The
next
command
can
be
initiated
at
t
14
,the
following
cycle
after
RDACK
drives
HIGH
(Read
is
complete).
3
.
The
Index
Bus
is
driven,
but
to
an
indeterminate
state.
4
.
For
Synchronous
Pipelined
Burst
SRAM,
the
CE
input
is
tied
LOW,
ADSP
is
tied
HIGH,
ADSC
Is
tied
LOW
and
the
OE
input
is
driven
by
the
IPC
CE
/OE
output.
5
.
RDACK
signal
can
be
valid
based
on
the
rising
edge
of
CLK2X,
at
time
tCRAK,
dependent
on
the
Pipeline
Delay
(PD)
value
that
is
programmed
into
the
System
Configuration
Register
(SCR).
This
signal
will
drive
for
2
CLK2X
cycles.
A
PD
value
of
3
is
shown
for
clarity.
Typically,
the
PD
would
be
set
to
2.
N
EXT
CO
M
A
N
D
ADDR
ESS
O
R
DAT
A
F
O
R
N
E
X
T
C
O
MMA
N
D
RE
QD
A
T
A
I5
32
5
d
rw
0
9
IN
D
E
X
IN
DX
MA
T
C
H
O
U
T
O
E
(4
)
SR
AM
REA
D
A
T
A
SRA
M
DA
TA
RD
A
C
K
(5
)
VA
LI
D
CM
D[
6
:4
]
W
E
HI
T
A
C
K
R
EAD
ADDR
ESS
CL
K
2
X
CC
L
K
(1
)
CM
D[
3
:0
]
t 1
t 2
t 3
t 4
t 5
t 6
t 7
t 8
t 0
t 9
t 10
t 11
t 12
t 13
t 14
t 15
t 16
RE
QST
B
T
h
e
nex
t
c
om
mand
c
annot
be
ini
tiated
until
R
e
ad
is
com
p
lete.
(s
e
note
2
)
(S
RA
M
R
E
A
D)
SR
A
M
R
E
AD
CO
M
A
N
D
t 17
NO
T
E
3
NO
T
E
3
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