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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 20/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Output Timing (with ZBT SRAM)
Timing Diagrams
NOTES:
1. CCLK is an internal signal not seen by the user.
2. The Index Bus is driven but to an indeterminate state.
3. Signal will drive LOW or HIGH depending on command; see sequence diagram for state.
4. This pin will be tied to the
CE input of ZBT and OE input will be tied LOW.
5. Refer to the SRAM datasheet for timing specifications.
6. HITACK and VALID signals can be valid based on the rising edge of CLK2X at time tCDV dependent on the Pipeline Delay (PD) value that
is programmed into the System Configuration Register (SCR). These signals will drive for 2 CLK2X cycles. A PD value of 3 is shown for
clarity. Typically, the PD would be set to 2.
7. RDACK signal can be valid based on the rising edge of CLK2X, at time tCRAK, dependent on the Pipeline Delay (PD)
value that is programmed into the System Configuration Register (SCR). This signal will drive for 2 CLK2X cycles. A PD value of 3 is shown
for clarity. Typically, the PD would be set to 2.
WE
SRAMDATA
HITACK
VALID
(MIN.)
tCDC
NOTE 3
H5325 d04
(MAX.)
tCDV
(MAX.)
tCDV
(MIN.)
tCDC
NOTE 3
RDACK(7)
(M A X .)
tCR AK
(MIN.)
tCRAK
SRAM READ or
WRITE DATA
(NOTE 5)
tCDV
(MIN.)
tCDV
(MAX.)
NOTE 3
CE/OE(4)
MATCHOUT
tCMDV
(MIN.)
(MAX.)
tCMDV
(MAX.)
tCDV
.
VALID INDEX
(MIN.)
tCDC
tCIV
(MAX.)
INDX
NOTE 2
CCLK(1)
CLK2X
t9
t10
t11
t12
t13
t14
t8
(OUTPUT TIMING for
all commands except
IPC Read and Write)
t15
t16
(MIN.)
tCDV
t18
t17
Pipeline Delay (PD)
(NOTE 6)
PD=0
PD=2
PD=3
PD=1
NOTE 3
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