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参数资料
| 型号： | IDT75T43100S66BS |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封装： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件页数： | 34/46页 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S66BS |
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4
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Functional Highlights continued
Functional Highlights
SRAM Interface
The IDT75T43100 provides all required address and control signals
for a glueless SRAM interface. When the user reads from or writes to the
external SRAM, the IPC provides a pipelined bypass path that takes the
20-bitAddress offtheRequestBusanddrivesthemtotheIndexBus. Refer
totheRequestBusFormatandtheIndexBusFormatformoreinformation.
TheASIC/FPGAhandlesthepipeliningofthedatatoandfromtheSRAM.
Control signal timing is programmed to accommodate standard ZBT
SRAMs, as well as Synchronous Pipelined Burst SRAMs. More detailed
information, along with how to configure this interface is discussed in the
“Initialization” section.
Registers
The IDT75T43100 utilizes 31 registers to provide additional features
and convenience. There are four basic types of registers supported:
- 4 Configuration Registers
- 4 Reply width Registers (RWRs)
- 8 Search Result Registers (SRRs)
- 15 Global Mask Registers (GMRs)
GMRs are provided to support Lookup instructions to mask individual
bits during a search. Initialization of the IPC uses the Configuration
Registers to define the timing of outputs and the SRAM interface configu-
ration. The Configuration registers are also used to specify certain
parameters when the IDT75T43100 is used in a multiple IPC implemen-
tation.
Furtherdetailsofeachtypeofregisterandtheirspecificimplementation
arediscussedinthesectionstitledundertheirrespectiveregistertype. Also
refer to the “Command Bus Format, GMR and SRR Select" and
“Initialization” sections for addressing and setup of these registers.
Width Capability
The IDT75T43100 is capable of performing lookups or comparisons
on data structures of 72 bits, 144 bits and 288 bits. The internal memory
bank of the device can be used in three standard width arrays, as shown
in Figure 1.2.
x
- 32K x72
x
- 16K x144
x
- 8K x288
Figure 1.2
The IDT75T43100 can also provide the address and control signals
for a read or write to an associated SRAM memory. The IPC pipelines
the address from the Request Bus to the Index Bus, driving it out to the
associated SRAM. The ASIC/FPGA handles the pipelining of the data to
and from the SRAM.
x
SRAM No Wait Read
An SRAM No Wait Read is a Read instruction to an external SRAM
that can be pipelined within a series of operations. A standard Read
instruction to an external SRAM requires the read to complete prior to
submitting the next instruction. However, the SRAM No Wait Read
instruction does not require the user to wait for a Read to complete. The
next instruction can be loaded sequentially on the following cycle.
x
Lookup
A lookup can be requested in 72-bit, 144-bit or 288-bit widths. A 36-bit
lookup can be accomplished by using GMRs 10 and 11, refer to the
application note (AN-270), "Implementing x36-bit Lookups". The Com-
mandBusidentifiesthespecificregisterstobeusedwithaparticularlookup.
All the instructions and associated commands are described in the
“Command Bus Format" and "GMR and SRR Select” sections. Please
refertothesesections forfurtherdefinitionof the instructioncode.
16K X 144
32K X 72
4K X 288
8K X 288
A5325 drw 03a
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